Datasheet

ADAS1000-3/ADAS1000-4 Data Sheet
Rev. A | Page 16 of 76
ADAS1000-3 Pin No. ADAS1000-4 Pin No.
Mnemonic Description
LQFP LFCSP LQFP LFCSP
44 32 44 32 SCLK Clock Input. Data is clocked into the shift register on a rising edge and clocked out on a
falling edge.
43 33 43 33 SDI Serial Data Input.
53 25 53 25
PD
Power-Down, Active Low.
45 31 45 31 SDO Serial Data Output. This pin is used for reading back register configuration data and for
the data frames.
42 34 42 34
DRDY
Digital Output. This pin indicates that conversion data is ready to be read back when
low, busy when high. When reading packet data, the entire packet must be read to
allow
DRDY
to return high.
54 24 54 24
RESET
Digital Input. This pin has an internal pull-up resistor. This pin resets all internal nodes to
their power-on reset values.
52 26 52 26 SYNC_GANG Digital Input/Output (Output on Master, Input on Slave). Used for synchronization
control where multiple devices are connected together. Powers up in high impedance.
36 40 36 40
GPIO0/
MCS
General-Purpose I/O or Master 128 kHz SPI
CS
.
37 39 37 39 GPIO1/MSCLK General-Purpose I/O or Master 128 kHz SPI SCLK.
38 38 38 38 GPIO2/MSDO General-Purpose I/O or Master 128 kHz SPI SDO.
39 37 39 37 GPIO3 General-Purpose I/O.
1, 3, 4, 5,
6, 13, 14,
16, 17,
32, 33,
48, 49,
62, 64
2, 3, 10,
11, 12,
13, 16
1, 13, 14,
16, 17, 32,
33, 48, 49,
64
2, 3 NC
No connect. Do not connect to these pins (see
Figure 7, Figure 8, Figure 9, and
Figure 10).
57 57 EPAD Exposed Pad. The exposed pad is on the top of the package; it is connected to the most
negative potential, AGND.