Datasheet

ADAS1000-3/ADAS1000-4 Data Sheet
Rev. A | Page 10 of 76
TIMING CHARACTERISTICS
Standard Serial Interface
AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock =
8.192 MHz. T
A
= −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at T
A
= 25°C.
Table 5.
IOVDD
Parameter
1
3.3 V 2.5 V 1.8 V Unit Description
Output Rate
2
2 128 kHz
Across specified IOVDD supply range; three programmable output data
rates available as configured in FRMCTL register (see Table 36) 2 kHz,
16 kHz, 128 kHz; use skip mode for slower rates.
SCLK Cycle Time 25 40 50 ns min See Table 20 for details on SCLK frequency vs. packet data/frame rates.
t
CSSA
8.5 9.5 12 ns min
CS
valid setup time to rising SCLK.
t
CSHA
3 3 3 ns min
CS
valid hold time to rising SCLK.
t
CH
8 8 8 ns min SCLK high time.
t
CL
8 8 8 ns min SCLK low time.
t
DO
8.5 11.5 20 ns typ SCLK falling edge to SDO valid delay; SDO capacitance of 15 pF.
11 19 24 ns max
t
DS
2 2 2 ns min SDI valid setup time from SCLK rising edge.
t
DH
2 2 2 ns min SDI valid hold time from SCLK rising edge.
t
CSSD
2 2 2 ns min
CS
valid setup time from SCLK rising edge.
t
CSHD
2 2 2 ns min
CS
valid hold time from SCLK rising edge.
t
CSW
25 40 50 ns min
CS
high time between writes (if used). Note that CS is an optional input,
it may be tied permanently low. See a full description in the Serial
Interfaces section.
t
DRDY_CS
2
0 0 0 ns min
DRDY
to CS setup time.
t
CSO
6 7 9 ns typ
Delay from CS
assert to SDO active.
RESET
Low Time
2
20 20 20 ns min
Minimum pulse width;
RESET
is edge triggered.
1
Guaranteed by characterization, not production tested.
2
Guaranteed by design, not production tested.
Figure 2. Data Read and Write Timing Diagram (CPHA = 1, CPOL = 1)
DB[30]DB[31] DB[0]DB[1]DB[29] DB[25] DB[24] DB[23]
SCLK
CS
SDI
t
CH
t
CL
t
CSSA
t
CSHA
t
CSHD
t
CSSD
t
DH
t
DS
t
CSW
SDO
t
DO
R/W
MSB LSB
DATAADDRESS
DO_25
DO_1 DO_0
DO_29DO_30DO_31DRDY
MSB
LSB
t
CSO
10997-002