Datasheet

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Low Power, Three Electrode

Electrocardiogram (ECG) Analog Front End

Data Sheet

ADAS1000-3/ADAS1000-4

Rev. A Document Feedback

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FEATURES

Biopotential signals in; digitized signals out

3 acquisition (ECG) channels and one driven lead

Can be ganged for 8 electrode + RLD using master

ADAS1000 or ADAS1000-1

AC and DC lead-off detection

Internal pace detection algorithm on 3 leads

Support for user’s own pace

Thoracic impedance measurement (internal/external path)

Selectable reference lead

Scalable noise vs. power control, power-down modes

Low power operation from

11 mW (1 lead), 15 mW (3 leads)

Lead or electrode data available

Supports AAMI EC11:1991/(R)2001/(R)2007, AAMI EC38

R2007, EC13:2002/(R)2007, IEC60601-1 ed. 3.0 b:2005,

IEC60601-2-25 ed. 2.0 :2011, IEC60601-2-27 ed. 2.0

b:2005, IEC60601-2-51 ed. 1.0 b: 2005

Fast overload recovery

Low or high speed data output rates

Serial interface SPI-/QSPI™-/DSP-compatible

56-lead LFCSP package (9 mm × 9 mm)

64-lead LQFP package (10 mm × 10 mm body size)

APPLICATIONS

ECG: monitor and diagnostic

Bedside patient monitoring, portable telemetry, Holter,

AED, cardiac defibrillators, ambulatory monitors, pace

maker programmer, patient transport, stress testing

GENERAL DESCRIPTION

The ADAS1000-3/ADAS1000-4 measure electro cardiac (ECG)

signals, thoracic impedance, pacing artifacts, and lead-on/off

status and output this information in the form of a data frame

supplying either lead/vector or electrode data at programmable

data rates. Its low power and small size make it suitable for

portable, battery-powered applications. The high performance

also makes it suitable for higher end diagnostic machines.

The ADAS1000-4 is a full-featured, 3-channel ECG including

respiration and pace detection, while the ADAS1000-3 offers

only ECG channels with no respiration or pace features.

The ADAS1000-3/ADAS1000-4 are designed to simplify

the task of acquiring and ensuring quality ECG signals.

They provide a low power, small data acquisition system for

biopotential applications. Auxiliary features that aid in better

quality ECG signal acquisition include: multichannel averaged

driven lead, selectable reference drive, fast overload recovery,

flexible respiration circuitry returning magnitude and phase

information, internal pace detection algorithm operating

on three leads, and the option of ac or dc lead-off detection.

Several digital output options ensure flexibility when monitor-

ing and analyzing signals. Value-added cardiac post processing

is executed externally on a DSP, microprocessor, or FPGA.

Because ECG systems span different applications, the

ADAS1000-3/ADAS1000-4 feature a power/noise scaling

architecture where the noise can be reduced at the expense

of increasing power consumption. Signal acquisition channels

may be shut down to save power. Data rates can be reduced to

save power.

To ease manufacturing tests and development as well as offer

holistic power-up testing, the ADAS1000-3

/ADAS1000-4

offer a suite of features, such as dc and ac test excitation via

the calibration DAC and CRC redundancy testing in addition

to readback of all relevant register address space.

The input structure is a differential amplifier input thereby

allowing users a variety of configuration options to best suit

their application.

The ADAS1000-3/ADAS1000-4 are available in two package

options: either a 56-lead LFCSP or a 64-lead LQFP package;

they are specified over −40°C to +85°C temperature range.

Summary of content (76 pages)

PAGE 1
Data Sheet Low Power, Three Electrode Electrocardiogram (ECG) Analog Front End ADAS1000-3/ADAS1000-4 FEATURES Biopotential signals in; digitized signals out 3 acquisition (ECG) channels and one driven lead Can be ganged for 8 electrode + RLD using master ADAS1000 or ADAS1000-1 AC and DC lead-off detection Internal pace detection algorithm on 3 leads Support for user’s own pace Thoracic impedance measurement (internal/external path) Selectable reference lead Scalable noise vs.
PAGE 2
ADAS1000-3/ADAS1000-4 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Evaluating Respiration Performance ....................................... 36 Applications ....................................................................................... 1 Pacing Artifact Detection Function (ADAS1000-4 Only) ... 36 General Description .........................................................................
PAGE 3
Data Sheet ADAS1000-3/ADAS1000-4 FUNCTIONAL BLOCK DIAGRAM REFIN REFOUT CAL_DAC_IO RLD_SJ RLD_OUT CM_IN CM_OUT/WCT DRIVEN LEAD AMP – VREF CALIBRATION DAC SHIELD SHIELD DRIVE AMP + AVDD IOVDD ADCVDD ADCVDD, DVDD 1.8V REGULATORS DVDD VCM_REF (1.
PAGE 4
ADAS1000-3/ADAS1000-4 Data Sheet SPECIFICATIONS AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock = 8.192 MHz. Decoupling for reference and supplies as noted in the Power Supply, Grounding, and Decoupling Strategy section. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C. For specified performance, internal ADCVDD and DVDD linear regulators have been used.
PAGE 5
Data Sheet ADAS1000-3/ADAS1000-4 Parameter Gain Error Gain Matching Min −1 Typ +0.01 Max +1 Unit % −2 −0.1 −0.5 +0.1 +0.02 +0.1 25 +2 +0.1 +0.5 % % % ppm/°C Gain Tempco1 Input Referred Noise1 Analog Lead Mode 6 10 12 11 12 14 16 100 Electrode Mode Digital Lead Mode Power Supply Sensitivity2 Analog Channel Bandwidth1 Dynamic Range 1 1 Signal-to-Noise Ratio COMMON-MODE INPUT Input Voltage Range Input Impedance2 Input Bias Current 0.
PAGE 6
ADAS1000-3/ADAS1000-4 Parameter RIGHT LEG DRIVE/DRIVEN LEAD Output Voltage Range RLD_OUT Short-Circuit Current Closed-Loop Gain Range2 Data Sheet Min Typ Max Unit 0.2 −5 ±2 AVDD − 0.2 +5 V mA 25 200 mV/ms Input Referred Noise1 8 μV p-p 1.5 MHz Lead-Off Current Accuracy High Threshold Level1 ±10 2.4 % V Low Threshold Level1 Threshold Accuracy AC LEAD-OFF 0.2 V 25 mV Frequency Range Lead-Off Current Accuracy REFIN Input Range2 Input Current 2.031 ±10 1.76 1.
PAGE 7
Data Sheet Parameter CLOCK_IO ADAS1000-3/ADAS1000-4 Min Operating Frequency2 Input Duty Cycle2 Output Duty Cycle2 DIGITAL INPUTS Input Low Voltage, VIL Input High Voltage, VIH Input Current, IIH, IIL Pin Capacitance2 DIGITAL OUTPUTS Output Low Voltage, VOL Output High Voltage, VOH Output Rise/Fall Time DVDD REGULATOR Output Voltage Available Current1 Short-Circuit Current Limit ADCVDD REGULATOR Output Voltage Short-Circuit Current Limit POWER SUPPLY RANGES2 AVDD IOVDD ADCVDD DVDD POWER SUPPLY CURRENTS AVD
PAGE 8
ADAS1000-3/ADAS1000-4 Parameter OTHER FUNCTIONS 4 Power Dissipation Respiration Shield Driver EXTERNALLY SUPPLIED ADCVDD AND DVDD AVDD Current ADCVDD Current DVDD Current INTERNALLY SUPPLIED ADCVDD AND DVDD AVDD Current Min Data Sheet Typ Max 7.6 150 Unit mW μW 1.9 1.7 3.6 2.5 1.7 0.9 3.7 3.7 5.5 4.5 4 3 mA mA mA mA mA mA 7.3 5.3 10.7 8.
PAGE 9
Data Sheet ADAS1000-3/ADAS1000-4 NOISE PERFORMANCE Table 3. Typical Input Referred Noise over a 0.5 sec Window (μV p-p) 1 Mode Analog Lead Mode 3 High Performance Mode Data Rate 2 GAIN 0 (×1.4) ±1 VCM GAIN 1 (×2.1) ±0.67 VCM GAIN 2 (×2.8) ±0.5 VCM GAIN 3 (×4.2) ±0.3 VCM 2 kHz (0.5 Hz to 40 Hz) 2 kHz (0.05 Hz to 150 Hz) 8 14 6 11 5 9 4 7.5 Typical values measured at 25°C, not subject to production test. Data gathered using the 2 kHz packet/frame rate is measured over 0.5 seconds.
PAGE 10
ADAS1000-3/ADAS1000-4 Data Sheet TIMING CHARACTERISTICS Standard Serial Interface AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock = 8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C. Table 5. Parameter1 Output Rate2 3.3 V 2 SCLK Cycle Time tCSSA tCSHA tCH tCL tDO tDS tDH tCSSD tCSHD tCSW 25 8.5 3 8 8 8.5 11 2 2 2 2 25 tDRDY_CS2 tCSO RESET Low Time2 0 6 20 2 1.
PAGE 11
Data Sheet ADAS1000-3/ADAS1000-4 tDRDY_CS DRDY tCH SCLK tCL tCSSA tCSSD tCSHD tCSHA CS tCSW tDH MSB SDI tCSO LSB DB[31] N DB[30] N DB[29] N DB[25] N DB[24] N R/W ADDRESS = 0x40 (FRAMES) DB[23] SDO DRDY DB[31] N+1 DB[1] LSB DB[31] N–1 DB[30] N–1 DB[24] DB[23] N–1 N–1 DB[25] N–1 DB[1] N–1 DB[1] N+1 DB[30] N+1 DB[0] N+1 DATA = NOP or 0x40 DATA MSB LSB MSB MSB DB[0] N–1 LSB DB[31] N tDO PREVIOUS DATA DB[30] N DB[1] N DB[0] N HEADER (FIRST WORD OF FRAME) 10997-003
PAGE 12
ADAS1000-3/ADAS1000-4 Data Sheet Secondary Serial Interface (Master Interface for Customer-Based Digital Pace Algorithm) ADAS1000-4 Only AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock = 8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C.
PAGE 13
Data Sheet ADAS1000-3/ADAS1000-4 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 7. Parameter AVDD to AGND IOVDD to DGND ADCVDD to AGND DVDD to DGND REFIN/REFOUT to REFGND ECG and Analog Inputs to AGND Digital Inputs to DGND REFIN to ADCVDD AGND to DGND REFGND to AGND ECG Input Continuous Current Storage Temperature Range Operating Junction Temperature Range Reflow Profile Junction Temperature ESD HBM FICDM Rating −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +2.5 V −0.3 V to +2.5 V −0.3 V to +2.1 V −0.
PAGE 14
ADAS1000-3/ADAS1000-4 Data Sheet AVDD CM_IN RLD_OUT RLD_SJ CM_OUT/WCT AVDD AGND AGND ADCVDD XTAL1 XTAL2 CLK_IO DVDD DGND NC NC 47 DGND 3 46 IOVDD NC 4 45 SDO NC 5 44 SCLK NC 6 43 SDI 2 NC PIN 1 REFGND 7 ADAS1000-3 42 DRDY REFOUT 8 64-LEAD LQFP 41 CS TOP VIEW (Not to Scale) 40 DGND 39 GPIO3 38 GPIO2/MSDO REFIN 9 ECG1_LA 10 ECG2_LL 11 37 GPIO1/MSCLK NC 13 36 GPIO0/MCS 35 IOVDD 34 DGND NC 16 33 NC NC NOTES 1.
PAGE 15
Data Sheet ADAS1000-3/ADAS1000-4 Table 9. Pin Function Descriptions ADAS1000-3 Pin No. LQFP LFCSP 18, 23, 15, 20, 58, 63 51, 56 ADAS1000-4 Pin No.
PAGE 16
ADAS1000-3/ADAS1000-4 Data Sheet ADAS1000-3 Pin No. LQFP LFCSP 44 32 ADAS1000-4 Pin No. LQFP LFCSP 44 32 Mnemonic SCLK 43 33 43 33 SDI Description Clock Input. Data is clocked into the shift register on a rising edge and clocked out on a falling edge. Serial Data Input. 53 25 53 25 PD Power-Down, Active Low. 45 31 45 31 SDO Serial Data Output. This pin is used for reading back register configuration data and for the data frames. 42 34 42 34 DRDY Digital Output.
PAGE 17
Data Sheet ADAS1000-3/ADAS1000-4 TYPICAL PERFORMANCE CHARACTERISTICS 8 15 10 INPUT REFERRED NOISE (µV) 4 2 0 –2 1 2 3 4 5 6 7 8 9 10 –5 –15 10997-039 0 TIME (Seconds) 8 0 1 2 3 4 5 6 7 8 9 10 Figure 14. Input Referred Noise for 0.5 Hz to 150 Hz Bandwidth, 2 kHz Data Rate, GAIN 3 (4.2) 25 0.5Hz TO 40Hz GAIN SETTING 3 = 4.2 DATA RATE = 2kHz 10 SECONDS OF DATA LA 150Hz LA 40Hz INPUT REFERRED NOISE (µV) 6 0.5Hz TO 150Hz GAIN SETTING 3 = 4.
PAGE 18
ADAS1000-3/ADAS1000-4 Data Sheet 0.121 0.215 AVDD = 3.3V AVDD = 3.3V 0.210 0.101 0.205 THRESHOLD (V) GAIN ERROR (%) 0.081 0.061 0.041 0.200 0.195 0.190 0.021 0.185 GAIN 1 GAIN 2 GAIN 3 GAIN SETTING Figure 17. Typical Gain Error vs. Gain 2.420 0 = 1.4 1 = 2.1 2 = 2.8 3 = 4.2 HIGH THRESHOLD (V) –0.20 AVDD = 3.3V 2.405 2.400 2.395 2.390 2.385 GAIN ERROR G0 GAIN ERROR G1 GAIN ERROR G2 GAIN ERROR G3 –0.35 –40 0 –20 20 40 60 2.380 2.375 –40 10997-046 –0.
PAGE 19
Data Sheet ADAS1000-3/ADAS1000-4 0 0 AVDD = 3.3V –1 –1 –2 –2 –4 GAIN (dB) GAIN (dB) –3 –5 –6 –3 –4 –7 –8 –5 –9 10 100 1k FREQUENCY (Hz) AVDD = 3.3V –6 1 0 0 –1 –2 –2 AVDD = 3.3V –3 –4 GAIN (dB) –5 –6 –4 –5 –6 –7 –7 –8 10 100 1k FREQUENCY (Hz) Figure 24. Filter Response with 250 Hz Filter Enabled, 2 kHz Data Rate; See Figure 68 for Digital Filter Overview 0 –9 10997-052 1 1 10 100 1k 10k 100k FREQUENCY (Hz) 10997-055 –8 –9 Figure 27.
PAGE 20
ADAS1000-3/ADAS1000-4 805 AVDD = 3.3V AVDD = 3.3V 800 AVDD SUPPLY CURRENT (µA) 1.3005 1.2995 1.2990 1.2985 1.2980 785 780 775 0 20 40 60 80 TEMPERATURE (°C) 765 –40 0 20 40 60 80 TEMPERATURE (°C) Figure 32. Typical AVDD Supply Current vs. Temperature in Standby Mode Figure 29. VCM_REF vs. Temperature 12.65 AVDD = 3.3V 3 ECG CHANNELS ENABLED INTERNAL LDO UTILIZED 12.45 HIGH PERFORMANCE/LOW NOISE MODE 12.60 12.40 12.55 CURRENT (mA) 12.50 12.35 12.
PAGE 21
Data Sheet ADAS1000-3/ADAS1000-4 0.517390 AVDD = 3.3V ECG PATH/DEFIB/CABLE IMPEDANCE = 0Ω PATIENT IMPEDANCE = 1kΩ 0.121140 RESPIRATION RATE = 10RESPPM RESPAMP = 11 = 60µA p-p RESPGAIN = 0011 = 4 0.121135 0.121130 0.121125 0.517375 0.517370 0.121120 0.517365 0.121115 0.517360 0 5 10 15 20 25 30 TIME (Seconds) Figure 35. Respiration with 100 mΩ Impedance Variation, Using Internal Respiration Paths and Measured with a 0 Ω Patient Cable 0.663160 0.663145 0.
PAGE 22
ADAS1000-3/ADAS1000-4 50 Data Sheet 150 LA LL RA AVDD = 3.3V 40 100 30 20 50 10 INL (µV/RTI) DNL ERROR (µV RTI) LA LL RA AVDD = 3.3V 0 –10 0 –50 –20 –30 –100 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 INPUT VOLTAGE (V) Figure 41. DNL Error vs. Input Voltage Range Across Electrodes at 25°C 50 30 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 INPUT VOLTAGE (V) Figure 44. INL vs.
PAGE 23
Data Sheet ADAS1000-3/ADAS1000-4 0 120 AVDD = 3.3V GAIN 0 DATA RATE = 2kHz FILTER SETTING = 150Hz –20 80 60 LOOP GAIN (dB) –60 –80 –100 –120 40 20 0 –140 –40 –160 –60 –180 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (Hz) Figure 47. FFT with 60 Hz Input Signal 150 –80 100m 1 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 10997-080 –20 10997-077 AMPLITUDE (dBFS) –40 100 Figure 50.
PAGE 24
ADAS1000-3/ADAS1000-4 Data Sheet APPLICATIONS INFORMATION monitor and diagnostic applications. Value-added cardiac post processing may be executed externally on a DSP, microprocessor, or FPGA. The ADAS1000-3/ADAS1000-4 are designed for operation in both low power, portable telemetry applications and line powered systems; therefore, the parts offer power/noise scaling to ensure suitability to these varying requirements.
PAGE 25
Data Sheet ADAS1000-3/ADAS1000-4 REFIN REFOUT CAL_DAC_IO RLD_SJ RLD_OUT CM_IN DRIVEN LEAD AMP – VREF CALIBRATION DAC SHIELD CM_OUT/WCT SHIELD DRIVE AMP + IOVDD ADCVDD, DVDD 1.8V REGULATORS ADCVDD DVDD + – VCM_REF (1.
PAGE 26
ADAS1000-3/ADAS1000-4 Data Sheet In a 3-lead system, the ADAS1000-3/ADAS1000-4 can be arranged to provide Lead I, Lead II, and Lead III data or electrode data directly via the serial interface at all frame rates. Note that in 128 kHz data rate, lead data is only available when configured in analog lead mode as shown in Table 11. Digital lead mode is not available for this data rate.
PAGE 27
Data Sheet ADAS1000-3/ADAS1000-4 The ADAS1000-3/ADAS1000-4 implementation uses a dccoupled approach, which requires that the front end be biased to operate within the limited dynamic range imposed by the relatively low supply voltage. The right leg drive loop performs this function by forcing the electrical average of all selected electrodes to the internal 1.3 V level, VCM_REF, maximizing each channel’s available signal range.
PAGE 28
ADAS1000-3/ADAS1000-4 Data Sheet Digital Lead Configuration and Calculation ELECTRODE/LEAD FORMATION AND INPUT STAGE CONFIGURATION The input stage of the ADAS1000-3/ADAS1000-4 can be arranged in several different manners. The input amplifiers are differential amplifiers and can be configured to generate the leads in the analog domain, before the ADCs. In addition to this, the digital data can be configured to provide either electrode or lead format under user control as described in Table 36.
PAGE 29
Data Sheet ADAS1000-3/ADAS1000-4 CM_OUT/WCT VCM = WCT = (LA + LL + RA)/3 COMMONMODE AMP ECGCTL 0x01[10] CHCONFIG = 1 FRMCTL 0x0A[4] DATAFMT = 0 DIFFERENTIAL INPUT – LEAD FORMAT LEAD I + (LA – RA) ADC AMP ECG1_LA – + AMP ECG2_LL LEAD III (LL – LA) ADC – + AMP ECG3_RA LEAD II (LL – RA)* ADC – *MULTIPLIED BY –1 IN DIGITAL MODE 10997-015 CM_IN for example RA COMMON ELECTRODE (CE) IN Figure 55.
PAGE 30
ADAS1000-3/ADAS1000-4 Data Sheet DEFIBRILLATOR PROTECTION ESIS FILTERING The ADAS1000-3/ADAS1000-4 do not include defibrillation protection on chip. Any defibrillation protection required by the application requires external components. Figure 58 and Figure 59 show examples of external defibrillator protection, which is required on each ECG channel, in the RLD path, and in the CM_IN path if using the CE input mode. Note that, in both cases, the total ECG path resistance is assumed to be 5 kΩ.
PAGE 31
Data Sheet ADAS1000-3/ADAS1000-4 common-mode block. If the physical connection to each electrode is buffered, these buffers are omitted for clarity. COMMON-MODE SELECTION AND AVERAGING The common-mode signal can be derived from any combination of one or more electrode channel inputs, the fixed internal common-mode voltage reference, VCM_REF, or an external source connected to the CM_IN pin.
PAGE 32
ADAS1000-3/ADAS1000-4 Data Sheet In some cases, adding lead compensation will prove necessary, while in others lag compensation may be more appropriate. The RLD amplifier’s summing junction is brought out to a package pin (RLD_SJ) to facilitate compensation. WILSON CENTRAL TERMINAL (WCT) The flexibility of the common-mode selection averaging allows the user to achieve a Wilson central terminal voltage from the ECG1_LA, ECG2_LL, ECG3_RA electrodes.
PAGE 33
Data Sheet ADAS1000-3/ADAS1000-4 The 10-bit calibration DAC can be used to correct channel gain errors (to ensure channel matching) or to provide several test tones. The options are as follows: A lead-off event sets a flag in the frame header word (see Table 52). Identification of which electrode is off is available as part of the data frame or as a register read from the leadoff status register (Register LOFF, see Table 46).
PAGE 34
ADAS1000-3/ADAS1000-4 Data Sheet pair of dedicated pins (EXT_RESP_LA, EXT_RESP_RA, or EXT_RESP_LL). Only one lead measurement can be made at one time. The respiration measurement path is not suited for use as additional ECG measurements because the internal configuration and demodulation do not align with an ECG measurement. RESPIRATION (ADAS1000-4 MODEL ONLY) The respiration measurement is performed by driving a high frequency (programmable from 46.
PAGE 35
Data Sheet ADAS1000-3/ADAS1000-4 External Respiration Path External Respiration Capacitors The EXT_RESP_xx pins are provided for use either with the ECG electrode cables or, alternatively, with a dedicated external sensor independent of the ECG electrode path. Additionally, the EXT_RESP_xx pins are provided such that the user can measure the respiration signal at the patient side of the RFI/ ESIS protection filters.
PAGE 36
ADAS1000-3/ADAS1000-4 1nF TO 10nF RESPDAC_LA Data Sheet 50kHz TO 56kHz ±1V 1kΩ 100Ω RESPIRATION DAC DRIVE + ve CABLE AND ELECTRODE IMPEDANCE < 1kΩ RESPIRATION MEASURE LA CABLE EXT_RESP_LA IN-AMP AND ANTI-ALIASING 10kΩ RA CABLE ADAS1000-4 OVERSAMPLED HPF SAR ADC GAIN 10kΩ LPF MAGNITUDE AND PHASE EXT_RESP_RA 1/2 OF AD8606 10kΩ 0.9V 1nF TO 10nF RESPDAC_RA 1kΩ 100Ω 46.5kHz TO 64kHz ±1V RESPIRATION DAC DRIVE – ve 1/2 OF AD8606 10997-025 REFOUT = 1.8V 10kΩ Figure 65.
PAGE 37
Data Sheet ADAS1000-3/ADAS1000-4 Some users may not wish to use three pace leads for detection. In this case, Lead II would be the vector of choice because this lead is likely to display the best pacing artifact. The other two pace instances can be disabled if not in use. The on-chip filtering contributes some delay to the pace signal (see the Pace Latency section).
PAGE 38
ADAS1000-3/ADAS1000-4 Data Sheet START ENABLE PACE DETECTION SELECT LEADS START PACE DETECTION ALGORITHM START PULSE WIDTH TIMER LOOK FOR TRAILING EDGE START NOISE FILTERS (if enabled) TRAILING EDGE DETECTED? NO YES NOISE FILTER PASSED? NO YES 2ms > PULSE WIDTH > 100µs NO YES 10997-026 FLAG PACE DETECTED UPDATE REGISTERS WITH WIDTH AND HEIGHT Figure 66. Overview of Pace Algorithm PACE PULSE PACELVLTH LEADING EDGE LEADING EDGE STOP PACEAMPTH PACEEDGETH RECHARGE PULSE Figure 67.
PAGE 39
Data Sheet ADAS1000-3/ADAS1000-4 Pace Amplitude Threshold Pace Validation Filter 2 This register (Address 0x07, see Table 33) can be used to set the minimum valid pace pulse amplitude: This filter is also used to reject sub threshold pulses such as MV pulses and inductive implantable telemetry systems. It is normally enabled and is controlled via the PACECTL register, Bit 10 (see Table 30). Filter 2 applies to all leads enabled for pace detection.
PAGE 40
ADAS1000-3/ADAS1000-4 Data Sheet delays the frame's ECG data relative to the pace pulse flag. These delays are summarized in Table 15 and must be taken into account to enable correct positioning of the pace event relative to the ECG data. While these experiments validate the pace algorithm over a confined set of circumstances and conditions, they do not replace end system verification of the pacer algorithm.
PAGE 41
Data Sheet ADAS1000-3/ADAS1000-4 AC LEAD-OFF DETECTION 2.048MHz PACE DETECTION 128kHz –3dB AT 13kHz ACLO CARRIER NOTCH 2kHz AVAILABLE DATA RATE CHOICE OF 1: 128kHz DATA RATE 16-BITS WIDE 128kHz 16kHz DATA RATE 24-BITS WIDE 18 USABLE BITS 16kHz –3dB AT 3.5kHz 16kHz 2kHz DATA RATE 24-BITS WIDE 19 USABLE BITS 2kHz –3dB AT 450Hz 40Hz 150Hz 250Hz (PROGRAMMABLE BESSEL ) ~7Hz CALIBRATION 31.25Hz DATA RATE 24-BITS WIDE ~22 USABLE BITS Figure 68. ECG Channel Filter Signal Flow Table 15.
PAGE 42
ADAS1000-3/ADAS1000-4 Data Sheet The ADAS1000-3/ADAS1000-4 have a high performance, low noise, on-chip 1.8 V reference for use in the ADC and DAC circuits. The REFOUT of one device is intended to drive the REFIN of the same device. The internal reference is not intended to drive significant external current; for optimum performance in gang operation with multiple devices, each device should use its own internal reference. An external 1.8 V reference can be used to provide the required VREF.
PAGE 43
Data Sheet ADAS1000-3/ADAS1000-4 Common Mode Right Leg Drive The ADAS1000-3/ADAS1000-4 have a dedicated CM_OUT pin serving as an output and a CM_IN pin as an input. In gang mode, the master device determines the common-mode voltage based on the selected input electrodes. This commonmode signal (on CM_OUT) can then be used by subsequent slave devices (applied to CM_IN) as the common-mode reference.
PAGE 44
RLD_OUT CM_IN REFOUT CAL_DAC_IO CM_OUT/ WCT SHIELD IOVDD AVDD DRIVEN LEAD AMP VREF CALIBRATION DAC SHIELD DRIVE AMP VCM_REF (1.3V) RESPIRATION DAC ADCVDD (optional) ADCVDD, DVDD 1.
PAGE 45
Data Sheet ADAS1000-3/ADAS1000-4 INTERFACING IN GANG MODE have the relevant synchronized data. Alternative methods might use individual controllers for each device or separate SDO paths. As shown in Figure 70, when using multiple devices, the user must collect the ECG data directly from each device. The example shown in Figure 71 illustrates one possibility of how to approach interfacing to a master and slave device.
PAGE 46
ADAS1000-3/ADAS1000-4 Data Sheet SERIAL INTERFACES The ADAS1000-3/ADAS1000-4 also provide an optional secondary serial interface that is capable of providing ECG data at the 128 kHz data rate for users wishing to apply their own digital pace detection algorithm. This is a master interface that operates with an SCLK of 20.48 MHz. STANDARD SERIAL INTERFACE The standard serial interface is LVTTL-compatible when operating from a 2.3 V to 3.6 V IOVDD supply.
PAGE 47
Data Sheet ADAS1000-3/ADAS1000-4 In the 128 kHz data rate, all write words are still 32-bit writes but the read words in the data packet are now 16 bits (upper 16 bits of register). There are no address bits, only data bits. Register space that is larger than 16 bits spans across 2 × 16-bit words (for example, pace and respiration). Data Frames/Packets The general data packet structure is shown in Table 18. Data can be received in two different frame formats.
PAGE 48
ADAS1000-3/ADAS1000-4 Data Sheet Internal operations are synchronized to the internal master clock at either 2.048 MHz or 1.024 MHz (ECGCTL[3]: HP = 1 and HP = 0, respectively, see Table 27). Because there is no guaranteed relationship between the internal clock and the SPI's SCLK signal, an internal handshaking scheme is used to ensure safe data transfer between the two clock domains.
PAGE 49
Data Sheet ADAS1000-3/ADAS1000-4 CRC Word Framed data integrity is provided by CRCs. For the 128 kHz frame rates, the 16-bit CRC-CCITT polynomial is used. For the 2 kHz and 16 kHz frame rates, the 24-bit CRC polynomial used. XTAL2 XTAL1 CLK_IO 10997-034 In both cases, the CRC residue is preset to all 1s and inverted before being transmitted. The CRC parameters are summarized in Table 23.
PAGE 50
ADAS1000-3/ADAS1000-4 Data Sheet SECONDARY SERIAL INTERFACE This second serial interface is an optional interface that can be used for the user’s own pace detection purposes. This interface contains ECG data at 128 kHz data rate only. If using this interface, the ECG data is still available on the standard interface discussed previously at lower rates with all the decimation and filtering applied. If this interface is inactive, it draws no power. Data is available in 16-bit words, MSB first.
PAGE 51
Data Sheet ADAS1000-3/ADAS1000-4 SPI OUTPUT FRAME STRUCTURE (ECG AND STATUS DATA) Three data rates are offered for reading ECG data: low speed 2 kHz/16 kHz rates for electrode/lead data (32-bit words) and a high speed 128 kHz for electrode/lead data (16-bit words).
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ADAS1000-3/ADAS1000-4 Data Sheet SPI REGISTER DEFINITIONS AND MEMORY MAP In 2 kHz and 16 kHz data rates, data takes the form of 32-bit words. Bit A6 to Bit A0 serve as word identifiers. Each 32-bit word has 24 bits of data. A third high speed data rate is also offered: 128 kHz with data in the form of 16-bit words (all 16 bits as data). Table 25.
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Data Sheet ADAS1000-3/ADAS1000-4 CONTROL REGISTERS DETAILS For each register address, the default setting is noted in a default column in addition to being noted in the function column by “(default)”; this format applies throughout the register map. Table 26. Serial Bit Assignment B31 R/W [B30:B24] Address bits [B23:B0] Data bits (MSB first) Table 27.
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ADAS1000-3/ADAS1000-4 Data Sheet Table 28. Lead-Off Control Register (LOFFCTL) Address 0x02, Reset Value = 0x000000 R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 Bit 23 22 21 [20:19] 18 Name LAPH LLPH RAPH Reserved CEPH R/W R/W R/W 0 0 0 17 16 15 LAACLOEN LLACLOEN RAACLOEN R/W R/W 0 0 [14:13] 12 Reserved CEACLOEN R/W R/W 0 00 [11:9] [8:7] Reserved ACCURRENT R/W R/W 00 000 [6:5] [4:2] Reserved DCCURRENT R/W 0 1 ACSEL R/W 0 0 LOFFEN Function AC lead-off phase.
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Data Sheet ADAS1000-3/ADAS1000-4 Table 29. Respiration Control Register (RESPCTL) Address 0x03, Reset Value = 0x000000 1 R/W Default R/W 0 Bit [23:17] 16 Name Reserved RESPALTFREQ R/W 0 15 RESPEXTSYNC R/W 0 14 RESPEXTAMP R/W 0 13 RESPOUT R/W 0 12 RESPCAP R/W 0000 [11:8] RESPGAIN [3:0] R/W 0 7 RESPEXTSEL R/W 00 [6:5] RESPSEL [1:0] R/W 00 [4:3] RESPAMP R/W 00 [2:1] RESPFREQ R/W 0 0 RESPEN 1 Function Reserved, set to 0.
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ADAS1000-3/ADAS1000-4 Data Sheet Table 30.
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Data Sheet ADAS1000-3/ADAS1000-4 Table 31. Common-Mode, Reference, and Shield Drive Control Register (CMREFCTL) Address 0x05, Reset Value = 0xE00000 R/W R/W R/W R/W Default 1 1 1 Bit 23 22 21 Name LACM LLCM RACM R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 [20:15] 14 13 12 [11:10] 9 Reserved LARLD LLRLD RARLD Reserved CERLD R/W 0 8 CEREFEN R/W 0000 [7:4] RLDSEL [3:0] R/W 0 3 DRVCM R/W 0 2 EXTCM R/W 0 1 RLDSEL R/W 0 0 SHLDEN Function Common-mode electrode select.
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ADAS1000-3/ADAS1000-4 Data Sheet Table 32.
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Data Sheet ADAS1000-3/ADAS1000-4 Table 33. Pace Amplitude Threshold Register (PACEAMPTH) Address 0x07, Reset Value = 0x242424 1 R/W R/W R/W R/W 1 Default 0010 0100 0010 0100 0010 0100 Bit [23:16] [15:8] [7:0] Name PACE3AMPTH PACE2AMPTH PACE1AMPTH Function Pace amplitude threshold Threshold = N × 2 × VREF/GAIN/216 ADAS1000-4 model only, ADAS1000-3 model does not contain these features. Table 34.
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ADAS1000-3/ADAS1000-4 Data Sheet Table 35. Calibration DAC Register (CALDAC) Address 0x09, Reset Value = 0x002000 1 R/W R/W Default 0 1 Bit [23:14] 13 Name Reserved CALCHPEN R/W 0 12 CALMODEEN R/W 0 11 CALINT R/W 0 10 CALDACEN R/W 0000000000 [9:0] CALDATA[9:0] 1 Function Reserved, set to 0. Calibration chop clock enable. The calibration DAC output (CAL_DAC_IO) can be chopped to lower 1/f noise. Chopping is performed at 256 kHz. 0 = disabled. 1 (default) = enabled.
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Data Sheet ADAS1000-3/ADAS1000-4 Table 36.
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ADAS1000-3/ADAS1000-4 Data Sheet Table 37.
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Data Sheet ADAS1000-3/ADAS1000-4 Table 40. Pace Edge Threshold Register (PACEEDGETH) Address 0x0E, Reset Value = 0x000000 1 R/W Default 0 0 0 R/W R/W R/W 1 Bit [23:16] [15:8] [7:0] Name PACE3EDGTH PACE2EDGTH PACE1EDGTH Function Pace edge trigger threshold 0 = PACEAMPTH/2 1 = VREF/gain/216 N = N × VREF/gain/216 ADAS1000-4 model only, ADAS1000-3 model does not contain these features. Table 41.
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ADAS1000-3/ADAS1000-4 Data Sheet Table 43. Read Pace Detection Data/Status Register (PACEDATA) Address 0x1A, Reset Value = 0x000000 1, 2, 3 R/W R Default 0 Bit 23 Name Pace 3 detected R 000 [22:20] Pace Channel 3 width R 0000 [19:16] Pace Channel 3 height R 0 15 Pace 2 detected R 000 [14:12] Pace Channel 2 width R 0000 [11:8] Pace Channel 2 height R 0 7 Pace 1 detected R 000 [6:4] Pace Channel 1 width R 0000 [3:0] Pace Channel 1 height Function Pace 3 detected.
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Data Sheet ADAS1000-3/ADAS1000-4 Table 46. Lead-Off Status Register (LOFF) Address 0x1D, Reset Value = 0x000000 R/W R Default 0 Bit 23 22 21 20 13 Name RLD lead-off Status LA lead-off status LL lead-off status RA lead-off status CELO R R 0 0 [19:14] 12 11 10 Reserved LAADCOR LLADCOR RAADCOR R 0 [9:0] Reserved Function Electrode connection status. If either dc or ac lead-off is enabled, these bits are the corresponding lead-off status.
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ADAS1000-3/ADAS1000-4 Data Sheet Table 48. Operating State Register (OPSTAT) Address 0x1F, Reset Value = 0x000000 1 R/W R R R Default 0 0 0 Bit [23:4] 3 2 Name Reserved Internal error Configuration status R 0 1 PLL lock R 0 0 PLL locked status 1 Function Reserved. Internal digital failure. This is set if an error is detected in the digital core. This bit is set after a reset indicating that the configuration has not been read yet. Once the configuration is set, this bit is ready. 0 = ready.
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Data Sheet ADAS1000-3/ADAS1000-4 Table 50. Read AC Lead-Off Amplitude Registers (LOAMxx) Address 0x31 to Address 0x33, Reset Value = 0x000000 1 R/W Default Bit [31:24] Name Address [7:0] R/W R 0 0 [23:16] [15:0] Reserved LOFFAM 1 Function 0x31: LA ac lead-off amplitude. 0x32: LL ac lead-off amplitude. 0x33: RA ac lead-off amplitude. Reserved. Measured amplitude.
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ADAS1000-3/ADAS1000-4 Data Sheet Table 52. Frame Header (FRAMES) Address 0x40, Reset Value = 0x800000 1 R/W R R Default 1 0 Bit 31 30 Name Marker Ready bit R 0 [29:28] Overflow [1:0] R 0 27 Fault R 0 26 Pace 3 detected R 0 25 Pace 2 detected R 0 24 Pace 1 detected R 0 23 Respiration R 0 22 Lead-off detected R 0 21 DC lead-off detected R 0 20 ADC out of range 0 [19:0] Reserved 1 Function Header marker, set to 1 for the header.
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Data Sheet ADAS1000-3/ADAS1000-4 INTERFACE EXAMPLES The following examples show register commands required to configure the ADAS1000-3/ADAS1000-4 devices into particular modes of operation and to start framing ECG data. Example 2: Enable Respiration and Stream Conversion Data (Applies to ADAS1000-4 Only) 1. Example 1: Initialize the Device for ECG Capture and Start Streaming Data 1. 2. 3. 4. 5.
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ADAS1000-3/ADAS1000-4 Data Sheet Example 4: Configure 150 Hz Test Tone Sine Wave on Each ECG Channel and Stream Conversion Data Example 5: Enable Pace Detection and Stream Conversion Data (Applies to ADAS1000-4 Only) 1. 1. 2. 3. 4. 5. 6. 7. Write 1 configures the CMREFCTL register to VCM_REF = 1.3 V (no electrodes contribute to VCM). RLD is enabled to RLD_OUT, and the shield amplifier enabled. Write 2 addresses the TESTTONE register to enable the 150 Hz sine wave onto all electrode channels.
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Data Sheet ADAS1000-3/ADAS1000-4 Example 6: Writing to Master and Slave Devices and Streaming Conversion Data This example uses the ADAS1000-3 as the slave device and the Master Configuration (ADAS1000) ADAS1000 as the master device to achieve a configuration with eight input electrodes and one right leg drive. 1. Slave Configuration (ADAS1000-3) 1. 2. 3. Write 1 configures the FRMCTL register to output five words per frame/packet.
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ADAS1000-3/ADAS1000-4 Data Sheet SOFTWARE FLOWCHART Figure 77 shows a suggested sequence of steps to be taken to interface to multiple devices. POWER UP ADAS1000 DEVICES WAIT FOR POR ROUTINE TO COMPLETE, 1.
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Data Sheet ADAS1000-3/ADAS1000-4 POWER SUPPLY, GROUNDING, AND DECOUPLING STRATEGY The ADAS1000-3/ADAS1000-4 should have ample supply decoupling of 0.01 μF on each supply pin located as close to the device pin as possible, ideally right up against the device. In addition, there should be one 4.7 μF capacitor for each of the power domains, AVDD and IOVDD, again located as close to the device as possible. IOVDD is best split from AVDD due to its noisy nature.
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ADAS1000-3/ADAS1000-4 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.60 0.42 0.24 0.60 0.42 0.24 0.275 43 PIN 1 INDICATOR 8.75 BSC SQ 1 0.50 BSC 6.05 5.95 SQ 5.85 *EXPOSED PAD 0.75 0.65 0.55 29 14 15 28 TOP VIEW BOTTOM VIEW 6.50 REF 0.70 MAX 0.65 NOM 12° MAX 0.05 MAX 0.01 NOM 0.30 0.23 0.18 0.20 REF 06-20-2012-A SEATING PLANE *FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure 78.
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Data Sheet ADAS1000-3/ADAS1000-4 ORDERING GUIDE Model 1 ADAS1000-3BSTZ ADAS1000-3BSTZ-RL ADAS1000-3BCPZ ADAS1000-3BCPZ-RL ADAS1000-4BSTZ ADAS1000-4BSTZ-RL ADAS1000-4BCPZ ADAS1000-4BCPZ-RL EVAL-ADAS1000SDZ EVAL-SDP-CB1Z Option Tray Reel, 1000 Tray Reel, 2500 Tray Reel, 1000 Tray Reel, 2500 Description 3 ECG Channels 3 ECG Channels, Pace Algorithm, Respiration Circuit ADAS1000 Evaluation Board System Demonstration Board (SDP), used as a controller board for data transfer via USB interface to PC 1 Temp
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ADAS1000-3/ADAS1000-4 Data Sheet NOTES ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10997-0-1/13(A) Rev.