Datasheet

ADA4940-1/ADA4940-2 Data Sheet
Rev. C | Page 24 of 32
Table 15 and Table 16 list several common gain settings, recommended resistor values, input impedances, and output noise density for both
balanced and unbalanced input configurations.
Table 15. Differential Ground-Referenced Input, DC-Coupled, R
L
= 1 kΩ (See Figure 64)
Nominal Gain (dB) R
F
(Ω) R
G
(Ω) R
IN, dm
(Ω) Differential Output Noise Density (nV/√Hz) RTI (nV/√Hz)
0 1000 1000 2000 11.3 11.3
6 1000 500 1000 15.4 7.7
10 1000 318 636 20.0 6.8
14 1000 196 392 27.7 5.5
Table 16. Single-Ended Ground-Referenced Input, DC-Coupled, R
S
= 50 Ω, R
L
= 1 kΩ (See Figure 65)
Nominal Gain (dB) R
F
(Ω) R
G
(Ω) R
T
(Ω) R
IN, se
(Ω) R
G1
(Ω)
1
Differential Output Noise Density (nV/√Hz) RTI (nV/√Hz)
0 1000 1000 52.3 1333 1025 11.2 11.2
6 1000 500 53.6 750 526 15.0 7.5
10 1000 318 54.9 512 344 19.0 6.3
14 1000 196 59.0 337 223 25.3 5
1
R
G1
= R
G
+ (R
S
||R
T
)
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
Even if the external feedback networks (R
F
/R
G
) are mismatched,
the internal common-mode feedback loop still forces the outputs
to remain balanced. The amplitudes of the signals at each output
remain equal and 180° out of phase. The input-to-output,
differential mode gain varies proportionately to the feedback
mismatch, but the output balance is unaffected.
As well as causing a noise contribution from V
OCM
, ratio-matching
errors in the external resistors result in a degradation of the ability
of the circuit to reject input common-mode signals, much the
same as for a four resistors difference amplifier made from a
conventional op amp.
In addition, if the dc levels of the input and output common-
mode voltages are different, matching errors result in a small
differential mode, output offset voltage. When G = 1, with a
ground-referenced input signal and the output common-mode
level set to 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worst-
case input CMRR of about 40 dB, a worst-case differential mode
output offset of 25 mV due to the 2.5 V level-shift, and no
significant degradation in output balance error.
CALCULATING THE INPUT IMPEDANCE OF AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 64, the input impedance (R
IN, dm
) between the inputs
(+D
IN
and −D
IN
) is simply R
IN, dm
= 2 × R
G
.
For an unbalanced, single-ended input signal (see Figure 65), the
input impedance is
















FG
F
G
seIN
RR
R
R
R
2
1
,
+V
S
ADA4940-1/
ADA4940-2
+IN
–IN
R
F
R
F
+D
IN
–D
IN
V
OCM
R
G
R
G
V
OUT, dm
08452-051
Figure 64. ADA4940-1/ADA4940-2 Configured for Balanced (Differential) Inputs
R
T
R
S
ADA4940-1/
ADA4940-2
+V
S
R
F
R
G
R
S
R
G
R
F
V
OCM
R
T
V
OUT, dm
08452-052
+IN
–IN
Figure 65. ADA4940-1/ADA4940-2 Configured for Unbalanced (Single-Ended)
Input
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the input resistor R
G1.