Datasheet

ADA4841-1/ADA4841-2
Rev. E | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
P
D
= Quiescent Power + (Total Drive Power − Load Power) Table 4.
Parameter Rating
Supply Voltage 12.6 V
Power Dissipation See Figure 5
Common-Mode Input Voltage −V
S
− 0.5 V to +V
S
+ 0.5 V
Differential Input Voltage
±1.8 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +125°C
Lead Temperature JEDEC J-STD-20
Junction Temperature 150°C
()
L
OUT
L
OUTS
SS
D
R
V
R
V
V
IVP
2
2
−
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
×+×=
RMS output voltages should be considered. If R
L
is referenced
to −V
S
, as in single-supply operation, the total drive power is
V
S
× I
OUT
. If the rms signal levels are indeterminate, consider the
worst case, when V
OUT
= V
S
/4 for R
L
to midsupply.
()
(
)
L
S
SS
D
R
V
IVP
2
4/
+×=
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
In single-supply operation with R
L
referenced to −V
S
, worst case
is V
OUT
= V
S
/2.
Airflow increases heat dissipation, effectively reducing θ
JA
.
In addition, more metal directly in contact with the package
leads and through holes under the device reduces θ
JA
.
Figure 5 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC_N
(125°C/W), the 6-lead SOT-23 (170°C/W), 8-lead MSOP
(145°C/W), and 8-lead LFCSP_WD (103°C/W) on a JEDEC
standard 4-layer board. θ
JA
values are approximations.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, θ
JA
is
specified for device soldered in circuit board for surface-mount
packages.
Table 5. Thermal Resistance
2.0
0
–55 125
05614-061
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (W)
1.5
1.0
0.5
–45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105 115
SOT-23
SOIC
MSOP
LFCSP
Package Type θ
JA
Unit
8-lead SOIC_N 125 °C/W
6-Lead SOT-23 170 °C/W
8-lead MSOP 130 °C/W
8-Lead LFCSP_WD 103 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4841-1/
ADA4841-2 is limited by the associated rise in junction
temperature (T
J
) on the die. At approximately 150°C, which is
the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
may change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
amplifiers. Exceeding a junction temperature of 150°C for an
extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the die
due to the amplifier’s drive at the output. The quiescent power is
the voltage between the supply pins (V
S
) times the quiescent
current (I
S
).