Datasheet

ADA4528-1/ADA4528-2 Data Sheet
Rev. D | Page 16 of 28
TIME (10µs/DIV)
0.5
0
–0.5
INPUT VOLTAGE (V)
–1
0
1
2
OUTPUT VOLTAGE (V)
V
SY
= ±1.25V
A
V
= –10
V
IN
= 187.5mV
R
L
= 10kΩ
C
L
= 100pF
09437-040
INPUT
OUTPUT
Figure 44. Positive Overload Recovery
TIME (10µs/DIV)
0.5
0
–0.5
INPUT VOLTAGE (V)
–2
–1
0
1
OUTPUT VO
LTAGE (V)
V
SY
= ±1.25V
A
V
= –10
V
IN
= 187.5mV
R
L
= 10kΩ
C
L
= 100pF
09437-039
INPUT
OUTPUT
Figure 45. Negative Overload Recovery
09437-044
TIME (10µs/DIV)
VOLTAGE (1V/DIV)
V
SY
= 2.5V
R
L
= 10kΩ
C
L
= 100pF
DUT A
V
= –1
INPUT
+7.5mV
0
–7.5mV
OUTPUT
ERROR BAND
POST GAIN = 5
Figure 46. Positive Settling Time to 0.1%
TIME (10µs/DIV)
0.5
0
–0.5
INPUT VOLTAGE (V)
–1
0
1
2
3
OUTPUT VO
LT
AGE (V)
V
SY
= ±2.5V
A
V
= –10
V
IN
= 375mV
R
L
= 10kΩ
C
L
= 100pF
09437-043
INPUT
OUTPUT
Figure 47. Positive Overload Recovery
TIME (10µs/DIV)
0.5
0
–0.5
INPUT VO
LTAGE (V)
–3
–2
–1
0
1
OUTPUT VOLT
AGE (V)
V
SY
= ±2.5V
A
V
= –10
V
IN
= 375mV
R
L
= 10kΩ
C
L
= 100pF
09437-042
INPUT
OUTPUT
Figure 48. Negative Overload Recovery
09437-047
TIME (10µs/DIV)
VOLTAGE (2V/DIV)
V
SY
= 5V
R
L
= 10kΩ
C
L
= 100pF
DUT A
V
= –1
INPUT
+20mV
0
–20mV
OUTPUT
ERROR BAND
POST GAIN = 5
Figure 49. Positive Settling Time to 0.1%