Datasheet

ADA4522-1/ADA4522-2/ADA4522-4 Data Sheet
Rev. F | Page 20 of 33
INPUT VOLTAGE (1V/DIV)
TIME (2µs/DIV)
V
SY
= ±2.5V
R
L
= 10k
C
L
= 50pF
DUT A
V
= –1
INPUT
OUTPUT
+10mV
0
–10mV
+1V
0
–1V
ERROR BAND
POST GAIN = 10
13168-046
Figure 66. Negative Settling Time to 0.1%, V
SY
= ±2.5 V
INPUT VOLTAGE (5V/DIV)
TIME (4µs/DIV)
V
SY
= ±15V AND ±27.5V
R
L
= 10k
C
L
= 50pF
DUT A
V
= –1
INPUT
OUTPUT
+50mV
0
–50mV
ERROR BAND
POST GAIN = 10
13168-047
+5V
0
–5V
Figure 67. Negative Settling Time to 0.1%, V
SY
= ±15 V and ±27.5 V
13168-166
0
10
20
30
40
50
60
100 1k 10k 100k 1M 10M
OUTPUT VOLTAGE SWING (V p-p)
FREQUENCY (Hz)
R
L
= 10k
A
V
= –1
V
IN
= ±26V
V
SY
= ±27.5V
V
IN
= ±13.5V
V
SY
= ±15V
V
IN
= ±1V
V
SY
= ±2.5V
Figure 68. Output Voltage Swing vs. Frequency
INPUT VOLTAGE (1V/DIV)
TIME (2µs/DIV)
V
SY
= ±2.5V
R
L
= 10k
C
L
= 50pF
DUT A
V
= –1
INPUT
OUTPUT
+10mV
0
–10mV
ERROR BAND
POST GAIN = 10
13168-048
+1V
0
–1V
Figure 69. Positive Settling Time to 0.1%, V
SY
= ±2.5 V
INPUT VOLTAGE (5V/DIV)
TIME (4µs/DIV)
V
SY
= ±15V AND ±27.5V
R
L
= 10k
C
L
= 50pF
DUT A
V
= –1
INPUT
OUTPUT
+50mV
0
–50mV
ERROR BAND
POST GAIN = 10
13168-049
+5V
0
–5V
Figure 70. Positive Settling Time to 0.1%, V
SY
= ±15 V and ±27.5 V
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