Datasheet

Data Sheet ADA4500-2
Rev. A | Page 19 of 24
THEORY OF OPERATION
RAIL-TO-RAIL OUTPUT
When processing a signal through an op amp to a load, it is often
desirable to have the output of the op amp swing as close to the
voltage supply rails as possible. For example, when an op amp is
driving an ADC and both the op amp and ADC are using the
same supply rail voltages, the op amp must drive as close to the
V+ and V− rails as possible so that all codes in the ADC are
usable. A non-rail-to-rail output can require as much as 1.5 V
or more between the output and the rails, thus limiting the
input dynamic range to the ADC, resulting in less precision
(number of codes) in the converted signal.
The ADA4500-2 can drive its output to within a few millivolts
of the supply rails (see the output voltage high and output voltage
low specifications in Table 1 and Table 2). The rail-to-rail output
maximizes the dynamic range of the output, increasing the range
and precision, and often saving the cost, board space, and added
error of the additional gain stages.
RAIL-TO-RAIL INPUT (RRI)
Using a CMOS nonrail-to-rail input stage (that is, a single
differential pair) limits the input voltage to approximately one gate-
source voltage (V
GS
) away from one of the supply lines. Because
V
GS
for normal operation is commonly more than 1 V, a single
differential pair, input stage op amp greatly restricts the allowable
input voltage. This can be quite limiting with low supply voltages
supplies. To solve this problem, RRI stages are designed to allow
the input signal to range to the supply voltages (see the input
voltage range specifications in Table 1 and Table 2). In the case
of the ADA4500-2, the inputs continue to operate 200 mV beyond
the supply rails (see Figure 7 and Figure 10).
ZERO CROSS-OVER DISTORTION
A typical rail-to-rail input stage uses two differential pairs (see
Figure 59). One differential pair amplifies the input signal when
the common-mode voltage is on the high end, and the other
pair amplifies the input signal when the common-mode voltage
is on the low end. This classic dual-differential pair topology
does have a potential drawback. If the signal level moves through
the range where one input stage turns off and the other input
stage turns on, noticeable distortion occurs. Figure 60 shows the
distortion in a typical plot of V
OS
(voltage difference between the
inverting and the noninverting input) vs. V
CM
(input voltage).
10617-103
VDD
M10
M9
M12
M11
M8
M7
M6
M5
VSS
BIAS5
BIAS4
BIAS3
–A
V
OUT
VSS
BIAS2
M3 M4
VDD
BIAS1
M1 M2
V
IN
+
V
IN
–
Figure 59. Typical PMOS-NMOS Rail-to-Rail Input Structure
10617-060
V
CM
(V)
V
OS
(µV)
0
–300
–100
100
300
1.5 3.5 5.0
1.00.5 2.5 4.54.03.02.0
–200
–150
–250
–50
0
50
150
200
250
V
SY
= 5V
T
A
= 25°C
Figure 60. Typical Input Offset Voltage (V
OS
) vs. Common-Mode Voltage (V
CM
)
Response in a Dual Differential Pair Input Stage Op Amp (Powered by a 5 V
Supply; Results of Approximately 100 Units per Graph Are Displayed)
This distortion in the offset error forces the designer to live with
the bump in the common-mode error or devise impractical ways
to avoid the crossover distortion areas, thereby narrowing the
common-mode dynamic range of the op amp.