Datasheet

ADA4432-1/ADA4433-1 Data Sheet
Rev. A | Page 24 of 28
OUTLINE DIMENSIONS
Figure 58. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-11)
Dimensions shown in millimeters
Figure 59. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
2.44
2.34
2.24
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
P
IN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.70
1.60
1.50
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO JEDEC STANDARDS MO-229-WEED
01-24-2011-B
COMPLIANT TO JEDEC STANDARDS MO-178-AB
10°
4°
0°
SEATING
PLANE
1.90
BSC
0.95 BSC
0.60
BSC
6 5
1 2 3
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0.15 MAX
0.05 MIN
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.30 MIN
0.55
0.45
0.35
PIN 1
INDICATOR
12-16-2008-A