Datasheet

ADA4320-1
Rev. A | Page 5 of 16
TIMING REQUIREMENTS
Full temperature range, V
CC
= 5 V, t
R
= t
F
= 4 ns, f
CLK
= 8 MHz, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit
Clock Pulse Width (t
WH
) 16 ns
Clock Period (t
C
) 32 ns
Setup Time SDATA vs. Clock (t
DS
) 5 ns
Setup Time DATEN vs. Clock (t
ES
)
16 ns
Hold Time SDATA vs. Clock (t
DH
) 5 ns
Hold Time DATEN vs. Clock (t
EH
)
3 ns
Input 10% to 90% Rise and Fall Times, SDATA, DATEN, Clock
10 ns
VALID DATA-WORD G1
MSB...LSB
VALID DATA-WORD G2
SDATA
CLK
TXEN
A
NALOG
OUTPUT
DATEN
t
DS
t
ES
t
EH
8 CLOCK CYCLES
GAIN TRANSFER (G1) GAIN TRANSFER (G2)
t
WH
t
C
SIGNAL AMPLITUDE (p-p)
08707-002
Figure 2. Serial Interface Timing
SDATA MSB MSB – 1 MSB – 2
CLK
VALID DATA BIT
t
DS
t
DH
08707-003
Figure 3. SDATA Timing