Datasheet

ADA4320-1
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Logic Inputs (TTL-/CMOS-Compatible Logic) ....................... 4
Timing Requirements .................................................................. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
Maximum Power Dissipation ..................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Applications Information .............................................................. 11
General Applications ................................................................. 11
Circuit Description .................................................................... 11
Programming .............................................................................. 11
Current Level and Gain Adjustment ....................................... 11
Power Saving Features ............................................................... 12
Input Bias, Impedance, and Termination ................................ 12
Output Bias, Impedance, and Termination ............................ 12
Power Supply ............................................................................... 12
Signal Integrity Layout Considerations ................................... 12
Initial Power-Up ......................................................................... 12
RAMP Pin Feature ..................................................................... 13
Output Transformer ................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
10/10—Rev. 0 to Rev. A
Changes to Product Title ................................................................. 1
Changes to Pin 14, Description, Table 6 ........................................ 7
Changes to Current Level and Gain Adjustment Section ......... 11
Changes to Output Bias, Impedance, and
Termination Section ....................................................................... 12
Changes to Figure 24 ...................................................................... 13
Changes to Ordering Guide .......................................................... 14
4/10—Revision 0: Initial Version