Datasheet

ADA4051-1/ADA4051-2
Rev. B | Page 17 of 20
COMPLIANT TO JEDEC STANDARDS MO-178-AA
121608-A
OUTLINE DIMENSIONS
10°
5°
0°
SEATING
PLANE
1.90
BSC
0.95 BSC
0.20
BSC
5
123
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0
.15 MAX
0
.05 MIN
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.35 MIN
0.55
0.45
0.35
Figure 61. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
1.00
0.90
0.70
0.46
0.36
0.26
2.20
2.00
1.80
2.40
2.10
1.80
1.35
1.25
1.15
COMPLIANT TO JEDEC STANDARDS MO-203-AA
072809-A
0.10 MAX
1.10
0.80
0.40
0.10
0.22
0.08
312
45
0.65 BSC
COPLANARITY
0.10
SEATING
PLANE
0.30
0.15
Figure 62. 5-Lead Thin Shrink Small Outline Transistor Package [SC-70]
(KS-5)
Dimensions shown in millimeters