Datasheet
AD9984A
Rev. 0 | Page 7 of 44
0
6476-020
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3217 18 19 20 21 22 23 24 25 26 27 28
29
30 31
33
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
49
64
63 62 61 60 59
58
57 56 55 54 53
52
51 50
GREEN 7
GREEN 8
GREEN 9
GREEN 6
GREEN 5
GREEN 4
GREEN 3
GREEN 2
GREEN 1
GREEN 0
BLUE 9
BLUE 8
BLUE 4
BLUE 5
BLUE 6
BLUE 7
BLUE 3
BLUE 2
BLUE 1
BLUE 0
V
DD
SDA
SCL
HSYNC1
VSYNC1
HSYNC0
VSYNC0
EXTCK/COAST
PV
D
FILT
PV
D
CLAMP
O/E FIELD
REFHI
REFLO
PWRDN
R
AIN1
R
AIN0
V
D
SOGIN1
G
AIN1
V
D
SOGIN0
G
AIN0
V
D
B
AIN0
B
AIN1
V
D
DAV
DD
RED 2
RED 1
RED 0
RED 3
RED 4
RED 5
RED 6
RED 7
RED 8
RED 9
V
DD
VSOUT/A0
HSOUT
SOGOUT
DATACK
AD9984A
TOP VIEW
(Not to Scale)
29
PIN 1
INDICATOR
Figure 3. 64-Lead LFCSP Pin Configuration
Table 4. Complete Pin Configuration List
Pin Number
Pin Type 80-Lead LQFP 64-Lead LFCSP Mnemonic Function Value
Inputs 14 43 R
AIN0
Channel 0 Analog Input for Converter R 0.0 V to 1.0 V
16 44 R
AIN1
Channel 1 Analog Input for Converter R 0.0 V to 1.0 V
6 37 G
AIN0
Channel 0 Analog Input for Converter G 0.0 V to 1.0 V
10 40 G
AIN1
Channel 1 Analog Input for Converter G 0.0 V to 1.0 V
2 34 BB
AIN0
Channel 0 Analog Input for Converter B 0.0 V to 1.0 V
4 35 BB
AIN1
Channel 1 Analog Input for Converter B 0.0 V to 1.0 V
70 26 HSYNC0 Horizontal Sync Input for Channel 0 3.3 V CMOS
68 24 HSYNC1 Horizontal Sync Input for Channel 1 3.3 V CMOS
71 27 VSYNC0 Vertical Sync Input for Channel 0 3.3 V CMOS
69 25 VSYNC1 Vertical Sync Input for Channel 1 3.3 V CMOS
8 38 SOGIN0 Input for Sync-on-Green Channel 0 0.0 V to 1.0 V
12 41 SOGIN1 Input for Sync-on-Green Channel 1 0.0 V to 1.0 V
72 28 EXTCK
1
External Clock Input 3.3 V CMOS
73 29 CLAMP External Clamp Input Signal 3.3 V CMOS
72 28 COAST
1
External PLL Coast Signal Input 3.3 V CMOS
17 45 PWRDN Power-Down Control 3.3 V CMOS