Datasheet

AD9983A
Rev. 0 | Page 35 of 44
OUTPUT CONTROL
0x1F—Bits[7:5] Output Mode
These bits choose between three options for the output mode.
In 4:4:4 mode, RGB is standard. In 4:2:2 mode, YCbCr is
standard, which allows a reduction in the number of output
pins from 24 to 16. In 4:4:4 DDR output mode, the data is in
RGB mode, but changes on every clock edge. The power-up
default setting is 100.
Table 51. Output Mode
Output Mode Result
100 4:4:4 RGB mode
101 4:2:2 YCbCr mode
110 4:4:4 DDR mode
0x1F—Bit[4] Primary Output Enable
This bit places the primary output in active or high impedance
mode. The power-up default setting is 1.
Table 52. Primary Output Enable
Select Result
0 Primary output is in high impedance mode
1 Primary output is enabled
0x1F—Bit[3] Secondary Output Enable
This bit places the secondary output in active or high
impedance mode.
The secondary output is designated when using either 4:2:2 or
4:4:4 DDR. In these modes, the data on the blue output channel is
the secondary output while the output data on the red and green
channels are the primary output. Secondary output is always a
DDR YCbCr data mode. See the
Output Formatter section and
Table 12. The power-up default setting is 0.
Table 53. Secondary Output Enable
Select Result
0 Secondary output is in high impedance mode
1 Secondary output is enabled
0x1F—Bits[2:1] Output Drive Strength
These two bits select the drive strength for all the high-speed
digital outputs (except VSOUT, A0, and the O/E field). Higher
drive strength results in faster rise/fall times and in general
makes it easier to capture data. Lower drive strength results in
slower rise/fall times and helps to reduce EMI and digitally
generated power supply noise. The power-up default setting is 10.
Table 54. Output Drive Strength
Output Drive Result
00 Low output drive strength
01 Medium low output drive strength
10 Medium high output drive strength
11 High output drive strength
0x1F—Bit[0] Output Clock Invert
This bit allows inversion of the output clock. The power-up
default setting is 0.
Table 55. Output Clock Invert
Select Result
0 Noninverted pixel clock
1 Inverted pixel clock
0x20—Bits[7:6] Output Clock Select
These bits allow selection of optional output clocks such as a
fixed 40 MHz clock, a 2× clock, a 90° phase-shifted clock, or the
normal pixel clock. The power-up default setting is 00.
Table 56. Output Clock Select
Select Result
00 Pixel clock
01 90° phase-shifted pixel clock
10 2× pixel clock
11 40 MHz internal clock
0x20—Bit[5] Output High Impedance
This bit puts all outputs (except SOGOUT) in a high impedance
state. The power-up default setting is 0.
Table 57. Output High Impedance
Select Result
0 Normal outputs
1 All outputs (except SOGOUT) in high impedance mode
0x20—Bit[4] SOG High Impedance
This bit allows the SOGOUT pin to be placed in high impedance
mode. The power-up default setting is 0.
Table 58. SOGOUT High Impedance
Select Result
0 Normal SOG output
1 SOGOUT pin is in high impedance mode
0x20—Bit[3] Field Output Polarity
This bit sets the polarity of the field output bit. The power-up
default setting is 1.
Table 59. Field Output Polarity
Select Result
0 Active low = even field; active high = odd field
1 Active low = odd field; active high = even field