Datasheet

AD9979
Rev. C | Page 46 of 56
Table 29. Timing Core Registers
Address
Data Bit
Content
Default
Value
Update
Type Name Description
30 [5:0] 0 SCK H1POSLOC H1 rising edge location.
[7:6] Unused Set unused bits to 0.
[13:8] 20 H1NEGLOC H1 falling edge location.
[15:14] 0 TESTMODE Test operation only. Set to 0.
[16] 1 H1POL H1 polarity control.
0 = inverse of Figure 19.
1 = no inversion.
[27:17] Unused Set unused bits to 0.
31 [5:0] 0 SCK H2POSLOC H2 rising edge location.
[7:6] Unused Set unused bits to 0.
[13:8] 20 H2NEGLOC H2 falling edge location.
[15:14] 0 TESTMODE Test operation only. Set to 0.
[16] 1 H2POL H2 polarity control.
0 = inverse of Figure 19.
1 = no inversion.
[27:17] Unused Set unused bits to 0.
32 [5:0] 0 SCK HLPOSLOC HL rising edge location.
[7:6] Unused Set unused bits to 0.
[13:8] 20 HLNEGLOC HL falling edge location.
[15:14] 0 TESTMODE Test operation only. Set to 0.
[16] 1 HLPOL HL polarity control.
0 = inverse of Figure 19.
1 = no inversion.
[27:17] Unused Set unused bits to 0.
33 [5:0] 0 SCK RGPOSLOC RG rising edge location.
[7:6] Unused Set unused bits to 0.
[13:8] 10 RGNEGLOC RG falling edge location.
[15:14] 0 TESTMODE Test operation only. Set to 0.
[16] 1 RGPOL RG polarity control.
0 = inverse of Figure 19.
1 = no inversion.
[27:17] Unused Set unused bits to 0.
34 [0] 0 SCK H1BLKRETIME Retime H1 HBLK to internal clock.
1
0 = no retime.
1 = enable retime.
[1] 0 H2BLKRETIME Retime H2 HBLK to internal clock.
1, 2
[2] 0 HLBLKRETIME Retime HL HBLK to internal clock.
1, 2
[3] 0 HL_HBLK_EN Enables HBLK for HL output.
0 = disable.
1 = enable.
[7:4] 0 HCLK_WIDTH Enables wide horizontal clocks during HBLK interval.
0 = disable (see Table 12).
[27:8] Unused Set unused bits to 0.