Datasheet

AD9979
Rev. C | Page 20 of 56
Increasing Horizontal Clock Width During HBLK
HBLK Mode 0 and HBLK Mode 1 allow the H1 to H4 pulse width
to increase during the HBLK interval. As shown in Figure 27,
the horizontal clock frequency can reduce by a factor of 1/2,
1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30 (see Table 12). To
enable this feature, the HCLK_WIDTH register (Address 0x34,
Bits[7:4]) is set to a value between 1 and 15. When this register
is set to 0, the wide HCLK feature is disabled.
The reduced frequency occurs only for H1 to H4 pulses that are
located within the HBLK area.
The HCLK_WIDTH feature is generally used in conjunction
with special HBLK patterns to generate vertical and horizontal
mixing in the CCD.
Note that the wide HCLK feature is available only in HBLK
Mode 0 and HBLK Mode 1, and not in HBLK Mode 2.
Table 12. HCLK Width Register
Name Length Description
HCLK_WIDTH 4 bits Controls H1 to H4 width during HBLK as a fraction of pixel rate.
0 = same frequency as pixel rate
1 = 1/2 pixel frequency, that is, doubles the HCLK pulse width
2 = 1/4 pixel frequency
3 = 1/6 pixel frequency
4 = 1/8 pixel frequency
5 = 1/10 pixel frequency
6 = 1/12 pixel frequency
7 = 1/14 pixel frequency
8 = 1/16 pixel frequency
9 = 1/18 pixel frequency
10 = 1/20 pixel frequency
11 = 1/22 pixel frequency
12 = 1/24 pixel frequency
13 = 1/26 pixel frequency
14 = 1/28 pixel frequency
15 = 1/30 pixel frequency
HBLK
HORIZONTAL CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHOWN),
1/4, 1/6, 1/8, 1/10, 1/12, AND SO ON, UP TO 1/30 USING HBLK_WIDTH REGISTER.
H1/H3
H2/H4
1/ f
PIX
2 × (1/ f
PIX
)
05957-029
Figure 27. Generating Wide Horizontal Clock Pulses During HBLK Interval