Datasheet

AD9979
Rev. C | Page 12 of 56
THEORY OF OPERATION
CCD
SERIAL
INTERFACE
D0 TO D13
DIGITAL IMAGE
PROCESSING
ASIC
V DRIVER
HD, VD
CLI
V1 > Vx, VSG1 > VSGx, SUBCK
H1 TO H4, HL, RG
AD9979
INTEGRATED
AFE + TD
GPO1, GPO2
05957-014
CCDINM/
CCDINP
Figure 12. Typical Application
Figure 12 shows the typical application for the AD9979. The
CCD output is processed by the AFE circuitry of the AD9979,
which consists of a CDS, a VGA, a black-level clamp, and an
ADC. The digitized pixel information is sent to the digital
image processor chip, which performs the post-processing and
compression. To operate the CCD, all CCD timing parameters
are programmed into the AD9979 from the system ASIC, through
the 3-wire serial interface. From the system master clock, CLI,
provided by the image processor or an external crystal, the
AD9979 generates the horizontal clocks of the CCD and all
internal AFE clocks.
All AD9979 clocks are synchronized with VD and HD inputs.
All of the horizontal pulses (CLPOB, PBLK, and HBLK) of the
AD9979 are programmed and generated internally.
The H drivers for H1 to H4 and RG are included in the AD9979,
allowing these clocks to be directly connected to the CCD.
The H-drive voltage of 3 V is supported in the AD9979.
Figure 13 and Figure 14 show the maximum horizontal and
vertical counter dimensions for the AD9979.These counters
control all internal horizontal and vertical clocking, to specify
line and pixel locations. The maximum HD length is 8191 pixels
per line, and the maximum VD length is 8192 lines per field.
13-BIT HORIZONTAL = 8192 PIXELS MAX
13-BIT VERTICAL = 8192 LINES MAX
0
5957-015
Figure 13. Maximum Dimensions for Vertical and Horizontal Counters
VD
HD
MAX VD LENGTH IS 8192 LINES
CLI
MAX HD LENGTH IS 8192 PIXELS
05957-016
Figure 14. Maximum VD and HD Dimensions