Datasheet

AD9974
Rev. A | Page 4 of 52
TIMING SPECIFICATIONS
X = A = B, C
L
= 20 pF, AVDD_X = DVDD_X = 1.8 V, f
CLI
= 65 MHz, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit Comments
MASTER CLOCK (CLI) See Figure 17
CLI Clock Period (t
CONV
) 15.38 ns
CLI High/Low Pulse Width (t
ADC
) 6.9 7.7 8.9 ns
Delay from CLI Rising Edge to Internal Pixel Position 0 (t
CLIDLY
) 5 ns
AFE
SHP Rising Edge to SHD Rising Edge (t
S1
) 6.9 7.7 8.5 ns See Figure 21
AFE Pipeline Delay 16 Cycles See Figure 22
CLPOB Pulse Width (Programmable) (t
COB
)
1
2 20 Pixels
HD Pulse Width t
CONV
ns
VD Pulse Width 1 HD period ns
SERIAL INTERFACE See Figure 52
Maximum SCK Frequency (f
SCLK
) 40 MHz
SL to SCK Setup Time (t
LS
) 10 ns
SCK to SL Hold Time (t
LH
) 10 ns
SDATA Valid to SCK Rising Edge Setup (t
DS
) 10 ns
SCK Rising Edge to SDATA Valid Hold (t
DH
) 10 ns
H-COUNTER RESET SPECIFICATIONS See Figure 49
HD Pulse Width t
CONV
ns
VD Pulse Width 1 HD period ns
VD Falling Edge to HD Falling Edge(t
VDHD
) 0 VD period − t
CONV
ns
HD Falling Edge to CLI Rising Edge(t
HDCLI
) 3 t
CONV
− 2 ns
CLI Rising Edge to SHPLOC (Internal Sample Edge) (t
CLISHP
) 3 t
CONV
− 2 ns
TIMING CORE SETTING RESTRICTIONS
Inhibited Region for SHP Edge Location (t
SHPINH
) (See Figure 21)
2
50 64/0 Edge location
Inhibited Region for SHP or SHD with Respect to H-Clocks
(See Figure 21)
3, 4 , 5, 6
RETIME = 0, MASK = 0 (t
SHDINH
) H × NEGLOC − 15 H × NEGLOC − 0 Edge location
RETIME = 0, MASK = 1 (t
SHDINH
) H × POSLOC − 15 H × POSLOC − 0 Edge location
RETIME = 1, MASK = 0 (t
SHPINH
) H × NEGLOC − 15 H × NEGLOC − 0 Edge location
RETIME = 1, MASK = 1 (t
SHPINH
) H × POSLOC − 15 H × POSLOC − 0 Edge location
Inhibited Region for DOUTPHASE Edge Location (t
DOUTINH
)
(See Figure 21)
SHDLOC + 0 SHDLOC + 15 Edge location
1
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
2
Only applies to slave mode operation. The inhibited area for SHP is needed to meet the timing requirements for t
CLISHP
for proper H-counter reset operation.
3
When 0x34[2:0] HxBLKRETIME bits are enabled, the inhibit region for SHD location changes to inhibit region for SHP location.
4
When sequence register 0x09[23:21] HBLK masking registers are set to 0, the H-edge reference becomes H × NEGLOC.
5
The H-clock signals that have SHP/SHD inhibit regions depend on the HCLK mode: Mode 1 = H1, Mode 2 = H1, H2, and Mode 3 = H1, H3.
6
These specifications apply when H1POL, H2POL, RGPOL, and HLPOL are all set to 1 (default setting).