Datasheet

AD9974
Rev. A | Page 17 of 52
Table 9. HCLK Modes, Selected by HCLKMODE Register (Address 0x23[7:5])
HCLK Mode Register Value Description
Mode 1 001 H1 edges are programmable, with H3 = H1 and H2 = H4 = inverse of H1.
Mode 2 010
H1 edges are programmable, with H3 = H1.
H2 edges are programmable, with H4 = H2.
Mode 3 100
H1 edges are programmable, with H2 = inverse of H1.
H3 edges are programmable, with H4 = inverse of H3.
Invalid Selection 000, 011, 101, 110, 111 Invalid register settings.
Table 10. H1, H2, RGCONTROL, DRVCONTROL, and SAMPCONTROL Register Parameters
Parameter Length (Bits) Range Description
Polarity 1 High/low
Polarity control for H1/H3 and RG.
0 = no inversion.
1 = inversion.
Positive Edge 6 0 to 63 edge location Positive edge location for H1/H3 and RG.
Negative Edge 6 0 to 63 edge location Negative edge location for H1/H3 and RG.
Sample Location 6 0 to 63 sample location Sampling location for SHP and SHD.
Drive Control 3 0 to 7 current steps Drive current for H1 to H4 and RG outputs, 0 to 7 steps of 4.3 mA each.
NOTES
1. EXAMPLE SHOWN FOR SHDLOC = 0.
2. HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
DOUTPHASE
CLK
DOUT
CCDIN
CLI
SHD
(INTERNAL)
ADC OUT
(INTERNAL)
NN+2N+1
N+3
N+13N+12N+11N+10N+9N+8N+7N+6N+5
N+4
N+14
SAMPLE PIXEL N
N+16 N+17N+15
N–14 N–4N–5N–6N–7N–8N–9N–10N–11N–12N–13 N–3 N–2 N–1 N N+1N–15N–16N–17
t
CLIDLY
PIPELINE LATENCY = 16 CYCLES
N–14 N–4N–5N–6N–7N–8N–9N–10N–11N–12N–13 N–3 N–2 N–1 N N+1N–15N–16N–17
t
DOUTINH
0
5955-022
Figure 22. Pipeline Delay of AFE Data Outputs
H-Driver and RG Outputs Digital Data Outputs
In addition to the programmable timing positions, the AD9974
features on-chip output drivers for the RG and H1 to H4 outputs.
These drivers are powerful enough to drive the CCD inputs
directly. The H-driver and RG-driver current can be adjusted
for optimum rise/fall time into a particular load by using the
drive strength control registers (Address 0x35). Use the register
to adjust the drive strength in 4.3 mA increments. The minimum
setting of 0 is equal to off or three-state, and the maximum setting
of 7 is equal to 30.1 mA.
For maximum system flexibility, the AD9974 uses the
DOUTPHASE registers (Address 0x37[11:0]) to select the
location for the start of each new pixel data value. Any edge
location from 0 to 63 can be programmed. These registers
determine the start location of the data output and the DCLK
rising edge with respect to the master clock input, CLI_X.
The pipeline delay through the AD9974 is shown in Figure 22.
After the CCD input is sampled by SHD, there is a 16-cycle
delay until the data is available.