Datasheet

AD9974
Rev. A | Page 14 of 52
THEORY OF OPERATION
CCD
SERIAL
INTERFACE
DOUT_A
DOUT_B
DIGITAL IMAGE
PROCESSING
ASIC
V DRIVER
HD_A, VD_A,
HD_B, VD_B
CLI_A, CLI_B
V1 > Vx, VSG1 > VSGx, SUBCK
H1_A TO H4_A, RG_A
H1_B TO H4_B, RG_B
AD9974
INTEGRATED
AFE + TD
CCDINP_A
CCDINM_A
05955-014
CCDINP_B
CCDINM_B
Figure 14. Typical Application
Figure 14 shows the typical system block diagram for the AD9974.
The charge-coupled device (CCD) output is processed by the
analog front-end (AFE) circuitry of the AD9974, consisting of a
CDS, VGA, black level clamp, and ADC. The digitized pixel
information is sent to the digital image processor chip, which
performs the postprocessing and compression. To operate the
CCD, all CCD timing parameters are programmed into the
AD9974 from the system ASIC through the 3-wire serial
interface. From the system master clock, CLI_X, which is provided
by the image processor or external crystal, the AD9974 generates
the horizontal clocks of the CCD and all internal AFE clocks.
All AD9974 clocks are synchronized with VD and HD inputs.
All of the AD9974 horizontal pulses (CLPOB, PBLK, and
HBLK) are programmed and generated internally.
The H-drivers for H1 to H4 and RG are included in the
AD9974, allowing these clocks to be directly connected to the
CCD. An H-driver voltage of 3 V is supported in the AD9974.
Figure 15 and Figure 16 show the maximum horizontal and
vertical counter dimensions for the AD9974. All internal horizontal
and vertical clocking is controlled by these counters, which specify
line and pixel locations. Maximum HD length is 8191 pixels per
line, and maximum VD length is 8191 lines per field.
13-BIT HORIZONTAL = 8192 PIXELS MAX
13-BIT VERTICAL = 8192 LINES MAX
MAXIMUM COUNTER DIMENSIONS
0
5955-015
Figure 15. Vertical and Horizontal Counters
VD
HD
MAX VD LENGTH IS 8192 LINES
CLI
MAX HD LENGTH IS 8192 PIXELS
05955-016
Figure 16. Maximum VD/HD Dimensions