Datasheet

AD9959
Rev. B | Page 7 of 44
Parameter Min Typ Max Unit Test Conditions/Comments
CMOS LOGIC OUTPUTS 1 mA load
V
OH
2.7 V
V
OL
0.4 V
POWER SUPPLY
Total Power Dissipation—All Channels On,
Single-Tone Mode
540 635 mW Dominated by supply variation
Total Power Dissipation—All Channels On,
with Sweep Accumulator
580 680 mW Dominated by supply variation
Total Power Dissipation—Full Power-Down 13 mW
I
AVDD
—All Channels On, Single-Tone Mode 155 180 mA
I
AVDD
—All Channels On, Sweep Accumulator, REFCLK
Multiplier and 10-Bit Output Scalar Enabled
160 185 mA
I
DVDD
—All Channels On, Single-Tone Mode 105 125 mA
I
DVDD
—All Channels On, Sweep Accumulator, REFCLK
Multiplier and 10-Bit Output Scalar Enabled
125 145 mA
I
DVDD_I/O
40 mA I
DVDD
= read
30 mA I
DVDD
= write
I
AVDD
Power-Down Mode 0.7 mA
I
DVDD
Power-Down Mode 1.1 mA
DATA LATENCY (PIPELINE DELAY) SINGLE-TONE MODE
2, 3
Frequency, Phase, and Amplitude Words to DAC
Output with Matched Latency Enabled
29 SYSCLK
s
Frequency Word to DAC Output with Matched
Latency Disabled
29 SYSCLK
s
Phase Offset Word to DAC Output with Matched
Latency Disabled
25 SYSCLK
s
Amplitude Word to DAC Output with Matched
Latency Disabled
17 SYSCLK
s
DATA LATENCY (PIPELINE DELAY) MODULATION MODE
3, 4
Frequency Word to DAC Output 34 SYSCLK
s
Phase Offset Word to DAC Output 29 SYSCLK
s
Amplitude Word to DAC Output 21 SYSCLK
s
DATA LATENCY (PIPELINE DELAY) LINEAR SWEEP MODE
3, 4
Frequency Rising/Falling Delta Tuning Word to DAC
Output
41 SYSCLK
s
Phase Offset Rising/Falling Delta Tuning Word to
DAC Output
37 SYSCLK
s
Amplitude Rising/Falling Delta Tuning Word to DAC
Output
29 SYSCLK
s
1
For the VCO frequency range of 160 MHz to 255 MHz, there is no guarantee of operation.
2
Data latency is referenced to I/O_UPDATE.
3
Data latency is fixed.
4
Data latency is referenced to a profile change.