Datasheet

AD9959
Rev. B | Page 43 of 44
Linear Sweep Ramp Rate (LSRR)—Address 0x07
Two bytes are assigned to this register.
Table 38. Description for LSRR
Bit Mnemonic Description
15:8 Falling sweep ramp rate (FSRR) Linear falling sweep ramp rate.
7:0 Rising sweep ramp rate (RSRR) Linear rising sweep ramp rate.
LSR Rising Delta Word (RDW)—Address 0x08
Four bytes are assigned to this register.
Table 39. Description for RDW
Bit Mnemonic Description
31:0 Rising delta word 32-bit rising delta-tuning word.
LSR Falling Delta Word (FDW)—Address 0x09
Four bytes are assigned to this register.
Table 40. Description for FDW
Bit Mnemonic Description
31:0 Falling delta word 32-bit falling delta-tuning word.