Datasheet
AD9959
Rev. B | Page 34 of 44
SCLK
SDIO_0
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CS
I7
(I0)
I6
(I1)
I5
(I2)
I4
(I3)
I3
(I4)
I2
(I5)
I1
(I6)
I0
(I7)
D7
(D0)
D6
(D1)
D5
(D2)
D4
(D3)
D3
(D4)
D2
(D5)
D1
(D6)
D0
(D7)
05246-025
Figure 43. Single-Bit Serial Mode Write Timing—Clock Stall Low
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CS
SCLK
SDIO_1
SDIO_0
D7
(D1)
D5
(D3)
D3
(D5)
D1
(D7)
D6
(D0)
D4
(D2)
D2
(D4)
D0
(D6)
I6
(I0)
I4
(I2)
I2
(I4)
I0
(I6)
I7
(I1)
I5
(I3)
I3
(I5)
I1
(I7)
05246-026
Figure 44. 2-Bit Serial Mode Write Timing—Clock Stall Low
INSTRUCTION CYCLE DATA TRANSFER CYCLE
SCLK
SDIO_1
SDIO_0
SDIO_2
SDIO_3
CS
I7
(I3)
I1
(I5)
I5
(I1)
I3
(I7)
I6
(I2)
I0
(I4)
I4
(I0)
I2
(I6)
D7
(D3)
D1
(D5)
D5
(D1)
D3
(D7)
D6
(D2)
D0
(D4)
D4
(D0)
D2
(D6)
05246-027
Figure 45. 4-Bit Serial Mode Write Timing—Clock Stall Low