Datasheet
AD9959
Rev. B | Page 22 of 44
In modulation mode, the amplitude frequency phase (AFP)
select bits (CFR[23:22]) and modulation level bits (FR1[9:8])
are programmed to configure the modulation type and level
(see Table 6 and Table 7). Note that the linear sweep enable bit
must be set to Logic 0 in direct modulation mode.
Table 6. Modulation Type Configuration
AFP Select
(CFR[23:22])
Linear Sweep Enable
(CFR[14])
Description
00 X Modulation disabled
01 0 Amplitude modulation
10 0 Frequency modulation
11 0 Phase modulation
Table 7. Modulation Level Selection
Modulation Level (FR1[9:8]) Description
00 Two-level modulation
01 Four-level modulation
10 Eight-level modulation
11 16-level modulation
When modulating, the RU/RD function can be limited based
on pins available for controlling the feature. The SDIO_x pins
are for RU/RD only, not for modulation.
Table 8. RU/RD Profile Pin Assignments
Ramp-Up/Ramp-Down
(RU/RD) (FR1[11:10])
Description
00 RU/RD disabled
01
Only Profile Pin P2 and Profile Pin P3
available for RU/RD operation
10
Only Profile Pin P3 available for RU/RD
operation
11
Only SDIO_1, SDIO_2, and SDIO_3
pins available for RU/RD operation;
this forces the serial I/O to be used
only in 1-bit mode
If the profile pins are used for RU/RD, Logic 0 is for ramp-up
and Logic 1 is for ramp-down.
Because of the number of available channels and limited data
pins, it is necessary to assign the profile pins and/or SDIO_1,
SDIO_2, and SDIO_3 pins to a dedicated channel. This is con-
trolled by the profile pin configuration (PPC) bits (FR1[14:12]).
Each of the following modulation descriptions incorporates
data pin assignments.
Two-Level Modulation—No RU/RD
The modulation level bits (FR1[9:8]) are set to 00 (two-level).
The AFP select bits (CFR[23:22]) are set to the desired modulation
type. The RU/RD bits (FR1[11:10]) and the linear sweep enable
bit (CFR[14]) are disabled. Table 9 displays how the profile pins
and channels are assigned.
As shown in Table 9, only Profile Pin P0 can be used to modulate
Channel 0. If frequency modulation is selected and Profile Pin
P0 is Logic 0, Channel Frequency Tuning Word 0 (Register
0x04) is chosen; if Profile Pin P0 is Logic 1, Channel Word 1
(Register 0x0A) is chosen.
Four-Level Modulation—No RU/RD
The modulation level bits are set to 01 (four-level). The AFP
select bits (CFR[23:22]) are set to the desired modulation type.
The RU/RD bits (FR1[11:10]) and the linear sweep enable bit
(CFR[14]) are disabled. Note that the other two channels not
being used should have their AFP select bits set to 00 due to the
lack of profile pins. Table 10 displays how the profile pins and
channels are assigned to each other.
For the conditions in Table 10, the profile (channel word)
register chosen is based on the 2-bit value presented to Profile
Pins [P0:P1] or Profile Pins [P2:P3].
For example, if PPC = 010, [P0:P1] = 11, and [P2:P3] = 01, then
the contents of the Channel Word 3 register of Channel 0 are
presented to the output of Channel 0 and the contents of the
Channel Word 1 register of Channel 3 are presented to the
output of Channel 3.
Table 9. Profile Pin Channel Assignments
Profile Pin Configuration (PPC) (FR1[14:12]) P0 P1 P2 P3 Description
XXX CH0 CH1 CH2 CH3 Two-level modulation, all channels, no RU/RD
Table 10. Profile Pin and Channel Assignments
Profile Pin Configuration (PPC) (FR1[14:12]) P0 P1 P2 P3 Description
000 CH0 CH0 CH1 CH1 Four-level modulation on CH0 and CH1, no RU/RD
001 CH0 CH0 CH2 CH2 Four-level modulation on CH0 and CH2, no RU/RD
010 CH0 CH0 CH3 CH3 Four-level modulation on CH0 and CH3, no RU/RD
011 CH1 CH1 CH2 CH2 Four-level modulation on CH1 and CH2, no RU/RD
100 CH1 CH1 CH3 CH3 Four-level modulation on CH1 and CH3, no RU/RD
101 CH2 CH2 CH3 CH3 Four-level modulation on CH2 and CH3, no RU/RD