4-Channel, 500 MSPS DDS with 10-Bit DACs AD9959 FEATURES Software-/hardware-controlled power-down Dual supply operation (1.8 V DDS core/3.
AD9959 TABLE OF CONTENTS Features .............................................................................................. 1 Linear Sweep Mode .................................................................... 25 Applications ....................................................................................... 1 Linear Sweep No-Dwell Mode ................................................. 26 Functional Block Diagram ..............................................................
AD9959 GENERAL DESCRIPTION frequency tuning word, 14 bits of phase offset, and a 10-bit output scale multiplier. The AD9959 consists of four direct digital synthesizer (DDS) cores that provide independent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct imbalances between signals due to analog processing, such as filtering, amplification, or PCB layout-related mismatches. Because all channels share a common system clock, they are inherently synchronized.
AD9959 SPECIFICATIONS AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; T = 25°C; RSET = 1.91 kΩ; external reference clock frequency = 500 MSPS (REFCLK multiplier bypassed), unless otherwise noted. Table 1.
AD9959 Parameter 75.1 MHz Analog Output (±50 kHz) 75.1 MHz Analog Output (±250 kHz) 75.1 MHz Analog Output (±1 MHz) 100.3 MHz Analog Output (±10 kHz) 100.3 MHz Analog Output (±50 kHz) 100.3 MHz Analog Output (±250 kHz) 100.3 MHz Analog Output (±1 MHz) 200.3 MHz Analog Output (±10 kHz) 200.3 MHz Analog Output (±50 kHz) 200.3 MHz Analog Output (±250 kHz) 200.3 MHz Analog Output (±1 MHz) PHASE NOISE CHARACTERISTICS Residual Phase Noise @ 15.
AD9959 Parameter Residual Phase Noise @ 100.3 MHz (fOUT) with REFCLK Multiplier Enabled 5× @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 15.1 MHz (fOUT) with REFCLK Multiplier Enabled 20× @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 40.1 MHz (fOUT) with REFCLK Multiplier Enabled 20× @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Residual Phase Noise @ 75.
AD9959 Parameter CMOS LOGIC OUTPUTS VOH VOL POWER SUPPLY Total Power Dissipation—All Channels On, Single-Tone Mode Total Power Dissipation—All Channels On, with Sweep Accumulator Total Power Dissipation—Full Power-Down IAVDD—All Channels On, Single-Tone Mode IAVDD—All Channels On, Sweep Accumulator, REFCLK Multiplier and 10-Bit Output Scalar Enabled IDVDD—All Channels On, Single-Tone Mode IDVDD—All Channels On, Sweep Accumulator, REFCLK Multiplier and 10-Bit Output Scalar Enabled IDVDD_I/O IAVDD Power-Down
AD9959 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature DVDD_I/O (Pin 49) AVDD, DVDD Digital Input Voltage (DVDD_I/O = 3.3 V) Digital Output Current Storage Temperature Range Operating Temperature Range Lead Temperature (10 sec Soldering) θJA θJC Rating 150°C 4V 2V −0.7 V to +4 V 5 mA –65°C to +150°C –40°C to +85°C 300°C 21°C/W 2°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
AD9959 56 55 54 53 52 51 50 49 48 47 46 45 44 43 DGND DVDD SYNC_CLK SDIO_3 SDIO_2 SDIO_1 SDIO_0 DVDD_I/O SCLK CS I/O_UPDATE DVDD DGND P3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIN 1 INDICATOR AD9959 TOP VIEW (Not to Scale) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P2 P1 P0 AVDD AGND AVDD CH1_IOUT CH1_IOUT AGND AVDD AGND AVDD CH0_IOUT CH0_IOUT AVDD AGND DAC_RSET AGND AVDD AGND AVDD REF_CLK REF_CLK CLK_MODE_SEL AGND AVDD LOOP_FILTER AGND 15 16 17 18 19 20 21 22
AD9959 Pin No. 24 Mnemonic CLK_MODE_SEL I/O1 I 27 LOOP_FILTER I 29 30 35 36 40 to 43 CH0_IOUT CH0_IOUT CH1_IOUT CH1_IOUT P0 to P3 O O O O I 46 I/O_UPDATE I 47 48 CS SCLK I I 49 50 51, 52 DVDD_I/O SDIO_0 SDIO_1, SDIO_2 I I/O I/O 53 SDIO_3 I/O 54 SYNC_CLK O 1 Description Control Pin for the Oscillator Section. Caution: Do not drive this pin beyond 1.8 V. When high (1.8 V), the oscillator section is enabled to accept a crystal as the REF_CLK source.
AD9959 TYPICAL PERFORMANCE CHARACTERISTICS RBW VBW SWT 20kHz 20kHz 1.6s RF ATT 20dB UNIT dB REF LVL 0dBm 0 A 1 –30 –30 –40 –40 –50 25MHz/DIV DELTA 1 (T1) –62.84dB 40.08016032MHz REF LVL 0dBm RBW VBW SWT STOP 250MHz 20kHz 20kHz 1.6s RF ATT 20dB UNIT dB START 0Hz 25MHz/DIV STOP 250MHz Figure 7. Wideband SFDR, fOUT = 15.1 MHz, fCLK = 500 MSPS REF Lv] 0dBm 0 A 1 05246-007 05246-004 START 0Hz DELTA 1 (T1) –60.13dB 75.15030060MHz RBW VBW SWT 20kHz 20kHz 1.
AD9959 REF LVL 0dBm 0 RBW VBW SWT DELTA 1 (T1) –84.73dB 254.50901604kHz 500Hz 500Hz 20s RF ATT 20dB UNIT dB 1 REF LVL 0dBm 0 A –10 –40 –40 (dB) –50 –60 –70 –70 –80 1AP –80 CENTER 1.1MHz 100kHz/DIV –90 –100 SPAN 1MHz Figure 10. NBSFDR, ±1 MHz, fOUT = 1.1 MHz, fCLK = 500 MSPS REF LVL 0dBm RBW VBW SWT DELTA 1 (T1) –84.10dB 120.24048096kHz 0 500Hz 500Hz 20s RF ATT 20dB UNIT dB CENTER 15.1MHz 100kHz/DIV SPAN 1MHz Figure 13. NBSFDR, ±1 MHz, fOUT = 15.
AD9959 –60 –100 75.1MHz –120 –130 100.3MHz –140 –150 40.1MHz 05246-034 –160 15.1MHz –170 10 100 1k 10k 100k 1M –65 SINGLE DAC POWER PLANE –70 –75 –80 –85 10M SEPARATE DAC POWER PLANES 05246-037 CHANNEL ISOLATION (dBc) PHASE NOISE (dBc/Hz) –110 25.3 50.3 Figure 16. Residual Phase Noise (SSB) with fOUT = 15.1 MHz, 40.1 MHz, 75.1 MHz, 100.3 MHz; fCLK = 500 MHz with REFCLK Multiplier Bypassed 150.3 200.3 175.3 4 CHANNELS ON 100.3MHz –110 75.1MHz –120 –130 40.
AD9959 APPLICATION CIRCUITS PULSE AD9959 ANTENNA RADIATING ELEMENTS FILTER FILTER CH1 FILTER FILTER CH2 FILTER FILTER CH3 FILTER FILTER 05246-042 CH0 LO REFCLK Figure 22.
AD9959 AD9510 CLOCK DISTRIBUTOR WITH DELAY EQUALIZATION REF_CLK AD9510 SYNCHRONIZATION DELAY EQUALIZATION FPGA DATA SYNC_OUT C1 S1 SYNC_IN AD9959 SYNC_CLK C2 S2 DATA AD9959 FPGA FPGA C3 S3 DATA AD9959 A3 (SLAVE 2) SYNC_CLK FPGA A2 (SLAVE 1) SYNC_CLK CENTRAL CONTROL A1 (MASTER) C4 S4 DATA AD9959 A4 (SLAVE 3) SYNC_CLK A_END 05246-044 CLOCK SOURCE Figure 25.
AD9959 PROGRAMMABLE 1 TO 32 DIVIDER AND DELAY ADJUST AD9515 AD9514 AD9513 AD9512 CH0 IMAGE AD9959 REFCLK AD9515 AD9514 AD9513 AD9512 CH2 CH3 n n LVPECL LVDS CMOS LVPECL LVDS CMOS LVPECL LVDS CMOS IMAGE AD9515 AD9514 AD9513 AD9512 n LVPECL LVDS CMOS n = DEPENDENT ON PRODUCT SELECTION 05246-040 CH1 AD9515 AD9514 AD9513 AD9512 n CLOCK OUTPUT SELECTION(S) Figure 28. Clock Generation Circuit Using the AD9512/AD9513/AD9514/AD9515 Series of Clock Distribution Chips Rev.
AD9959 EQUIVALENT INPUT AND OUTPUT CIRCUITS DVDD_I/O = 3.3V INPUT OUTPUT 05246-002 AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING DIODES MAY COUPLE DIGITAL NOISE ON POWER PINS. Figure 29. CMOS Digital Inputs CHx_IOUT TERMINATE OUTPUTS INTO AVDD. DO NOT EXCEED VOLTAGE COMPLIANCE OF OUTPUTS. 05246-032 CHx_IOUT Figure 30. DAC Outputs AVDD 1.5kΩ Z Z 1.5kΩ OSC REF_CLK AVDD AMP REF_CLK INPUTS ARE INTERNALLY BIASED AND NEED TO BE AC-COUPLED. OSC INPUTS ARE DC-COUPLED. Figure 31.
AD9959 THEORY OF OPERATION DDS CORE DIGITAL-TO-ANALOG CONVERTER The AD9959 has four DDS cores, each consisting of a 32-bit phase accumulator and phase-to-amplitude converter. Together, these digital blocks generate a digital sine wave when the phase accumulator is clocked and the phase increment value (frequency tuning word) is greater than 0. The phase-to-amplitude converter simultaneously translates phase information to amplitude information by a cos(θ) operation.
AD9959 MODES OF OPERATION There are many combinations of modes (for example, singletone, modulation, linear sweep) that the AD9959 can perform simultaneously. However, some modes require multiple data pins, which can impose limitations. The following guidelines can help determine if a specific combination of modes can be performed simultaneously by the AD9959.
AD9959 REFERENCE CLOCK MODES The AD9959 supports multiple reference clock configurations to generate the internal system clock. As an alternative to clocking the part directly with a high frequency clock source, the system clock can be generated using the internal, PLL-based reference clock multiplier. An on-chip oscillator circuit is also available for providing a low frequency reference signal by connecting a crystal to the clock input pins.
AD9959 39pF 25MHz XTAL When FR1[6] = 1 and the PWR_DWN_CTL input pin is high, the AD9959 is put into full power-down mode. In this mode, all functions are powered down. This includes the DAC and PLL, which take a significant amount of time to power up. When the PLL is bypassed, the PLL is shut down to conserve power. REF_CLK PIN 23 05246-019 REF_CLK PIN 22 39pF Figure 35.Crystal Input Configuration SCALABLE DAC REFERENCE CURRENT CONTROL MODE RSET is common to all four DACs.
AD9959 Because of the number of available channels and limited data pins, it is necessary to assign the profile pins and/or SDIO_1, SDIO_2, and SDIO_3 pins to a dedicated channel. This is controlled by the profile pin configuration (PPC) bits (FR1[14:12]). Each of the following modulation descriptions incorporates data pin assignments.
AD9959 Eight-Level Modulation—No RU/RD For the conditions in Table 12, the profile register chosen is based on the 4-bit value presented to Profile Pins [P0:P3]. For example, if PPC = X11 and [P0:P3] = 1110, the contents of the Channel Word 14 register of Channel 3 is presented to the output of Channel 3. The modulation level bits (FR1[9:8]) are set to 10 (eight-level). The AFP select bits (CFR[23:22]) are set to a nonzero value.
AD9959 MODULATION USING SDIO_x PINS FOR RU/RD For RU/RD bits = 11, the SDIO_1, SDIO_2, and SDIO_3 pins are available for RU/RD. In this mode, modulation levels of 2, 4, and 16 are available. Note that the serial I/O port can be used only in 1-bit serial mode. Two-Level Modulation Using SDIO Pins for RU/RD Table 15. Profile Pin and Channel Assignments in Two-Level Modulation (RU/RD Enabled) Profile Pin Config.
AD9959 Setting the Slope of the Linear Sweep Linear sweep mode enables the user to sweep frequency, phase, or amplitude from a starting point (S0) to an endpoint (E0). The purpose of linear sweep mode is to provide better bandwidth containment compared to direct modulation by replacing greater instantaneous changes with more gradual, user-defined changes between S0 and E0.
AD9959 This load and countdown operation continues for as long as the timer is enabled. However, the count can be reloaded before reaching 1 by either of the following two methods: When the profile pin transitions from high to low, the FDW is applied to the input of the sweep accumulator and the FSRR bits are loaded into the sweep rate timer. • The FDW accumulates at the rate given by the falling sweep ramp rate (FSRR) until the output is equal to the CFTW0 register (Register 0x04) value.
AD9959 fOUT B FTW1 A FTW0 B B A A SINGLE-TONE MODE P0 = 0 P0 = 1 P0 = 0 P0 = 1 P0 = 0 P0 = 1 05246-047 TIME LINEAR SWEEP MODE ENABLE—NO-DWELL BIT SET Figure 38. Linear Sweep Mode (No-Dwell Enabled) fOUT B FTW1 A FTW0 TIME P0 = 0 LINEAR SWEEP MODE P0 = 1 P0 = 0 AT POINT A: LOAD RISING RAMP RATE REGISTER, APPLY RDW<31:0> AT POINT B: LOAD FALLING RAMP RATE REGISTER, APPLY FDW<31:0> 05246-048 SINGLE-TONE MODE Figure 39.
AD9959 OUTPUT AMPLITUDE CONTROL MODE A special feature of this mode is that the maximum output amplitude allowed is limited by the contents of the amplitude scale factor (ACR[9:0]). This allows the user to ramp to a value less than full scale. The 10-bit scale factor (multiplier) controls the ramp-up and ramp-down (RU/RD) time of an on/off emission from the DAC. In burst transmissions of digital data, it reduces the adverse spectral impact of abrupt bursts of data.
AD9959 SYNCHRONIZING MULTIPLE AD9959 DEVICES The AD9959 allows easy synchronization of multiple AD9959 devices. At power-up, the phase of SYNC_CLK can be offset between multiple devices. To correct for the offset and align the SYNC_CLK edges, there are three methods (one automatic mode and two manual modes) of synchronizing the SYNC_CLK edges. These modes force the internal state machines of multiple devices to a known state, which aligns the SYNC_CLK edges. Table 24.
AD9959 If the setup time between these signals is met, then constant latency (pipeline) to the DAC output exists. For example, if repetitive changes to phase offset via the SPI port is desired, the latency of those changes to the DAC output is constant; otherwise, a time uncertainty of one SYNC_CLK period is present. I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK RELATIONSHIPS I/O_UPDATE and SYNC_CLK are used together to transfer data from the serial I/O buffer to the active registers in the device.
AD9959 SERIAL I/O PORT Three of the four data pins (SDIO_1, SDIO_2, SDIO_3) can be used for functions other than serial I/O port operation. These pins can also be used to initiate a ramp-up or ramp-down (RU/RD) of the 10-bit amplitude output scalar. In addition, SDIO_3 can be used to provide the SYNC_I/O function that resynchronizes the serial I/O port controller if it is out of proper sequence.
AD9959 Each set of communication cycles does not require an I/O update to be issued. The I/O update transfers data from the I/O port buffer to active registers. The I/O update can be sent for each communication cycle or can be sent when all serial operations are complete. However, data is not active until an I/O update is sent, with the exception of the channel enable bits in the channel select register (CSR). These bits do not require an I/O update to be enabled.
AD9959 SERIAL I/O MODES OF OPERATION The following are the four programmable modes of serial I/O port operation: • • • • Single-bit serial 2-wire mode (default mode) Single-bit serial 3-wire mode 2-bit serial mode 4-bit serial mode (SYNC_I/O not available) Table 26 displays the function of all six serial I/O interface pins, depending on the mode of serial I/O operation programmed. Table 26. Serial I/O Port Pin Function vs.
AD9959 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS I6 (I1) I5 (I2) I4 (I3) I3 (I4) I2 (I5) I1 (I6) I0 (I7) D7 (D0) D6 (D1) D5 (D2) D4 (D3) D3 (D4) D2 (D5) Figure 43. Single-Bit Serial Mode Write Timing—Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO_1 I7 (I1) I5 (I3) I3 (I5) I1 (I7) D7 (D1) D5 (D3) D3 (D5) D1 (D7) SDIO_0 I6 (I0) I4 (I2) I2 (I4) I0 (I6) D6 (D0) D4 (D2) D2 (D4) D0 (D6) Figure 44.
AD9959 DATA TRANSFER CYCLE INSTRUCTION CYCLE CS I7 (I0) SDIO_0 I6 (I1) I5 (I2) I4 (I3) I3 (I4) I2 (I5) I1 (I6) I0 (I7) D7 (D0) D6 (D1) D5 (D2) D4 (D3) D3 (D4) D2 (D5) D1 (D6) D0 (D7) 05246-028 SCLK Figure 46. Single-Bit Serial Mode (2-Wire) Read Timing—Clock Stall High DATA TRANSFER CYCLE INSTRUCTION CYCLE CS SCLK I6 (I1) I5 (I2) I4 (I3) I3 (I4) I2 (I5) I1 (I6) I0 (I7) DON'T CARE SDO D7 (D0) (SDIO_2 PIN) D6 (D1) D5 (D2) D4 (D3) D3 (D4) D2 (D5) Figure 47.
AD9959 REGISTER MAPS AND BIT DESCRIPTIONS REGISTER MAPS Table 28.
AD9959 Table 29. Channel Register Map Register Name (Serial Address) Channel Function Register1 (CFR) (0x03) Bit Range [23:16] [15:8] [7:0] Channel Frequency Tuning Word 01 (CFTW0) (0x04) Channel Phase Offset Word 01 (CPOW0) (0x05) Amplitude Control Register (ACR) (0x06) Linear Sweep Ramp Rate1 (LSRR) (0x07) LSR Rising Delta Word1 (RDW) (0x08) LSR Falling Delta Word1 (FDW) (0x09) Bit 7 (MSB) Bit 6 Amplitude freq.
AD9959 Table 30.
AD9959 DESCRIPTIONS FOR CONTROL REGISTERS Channel Select Register (CSR)—Address 0x00 One byte is assigned to this register. The CSR determines if channels are enabled or disabled by the status of the four channel enable bits. All four channels are enabled by their default state. The CSR also determines which serial mode of operation is selected. In addition, the CSR offers a choice of MSB first or LSB first format. Table 31.
AD9959 Bit 5 Mnemonic SYNC_CLK disable 4 DAC reference power-down 3:2 1 Open Manual hardware sync 0 Manual software sync Description 0 = the SYNC_CLK pin is active (default). 1 = the SYNC_CLK pin assumes a static Logic 0 state (disabled). In this state, the pin drive logic is shut down. However, the synchronization circuitry remains active internally to maintain normal device operation. 0 = DAC reference is enabled (default). 1 = DAC reference is powered down.
AD9959 DESCRIPTIONS FOR CHANNEL REGISTERS Channel Function Register (CFR)—Address 0x03 Three bytes are assigned to this register. Table 34.
AD9959 Channel Frequency Tuning Word 0 (CFTW0)—Address 0x04 Four bytes are assigned to this register. Table 35. Description for CFTW0 Bit 31:0 Mnemonic Frequency Tuning Word 0 Description Frequency Tuning Word 0 for each channel. Channel Phase Offset Word 0 (CPOW0)—Address 0x05 Two bytes are assigned to this register. Table 36.
AD9959 Linear Sweep Ramp Rate (LSRR)—Address 0x07 Two bytes are assigned to this register. Table 38. Description for LSRR Bit 15:8 7:0 Mnemonic Falling sweep ramp rate (FSRR) Rising sweep ramp rate (RSRR) Description Linear falling sweep ramp rate. Linear rising sweep ramp rate. LSR Rising Delta Word (RDW)—Address 0x08 Four bytes are assigned to this register. Table 39. Description for RDW Bit 31:0 Mnemonic Rising delta word Description 32-bit rising delta-tuning word.
AD9959 OUTLINE DIMENSIONS 8.00 BSC SQ 0.60 MAX 0.50 0.40 0.30 12° MAX SEATING PLANE 29 28 15 14 0.25 MIN 6.50 REF 0.80 MAX 0.65 TYP 0.50 BSC 6.25 6.10 SQ 5.95 EXPOSED PAD (BOTTOM VIEW) 7.75 BSC SQ 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN ELECTRICAL CONNECTION AND MUST BE SOLDERED TO GROUND. COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2 061008-A TOP VIEW PIN 1 INDICATOR 56 1 43 42 PIN 1 INDICATOR 1.00 0.85 0.80 0.30 0.23 0.18 0.
