Datasheet

AD9958 Data Sheet
Rev. B | Page 6 of 44
Parameter Min Typ Max Unit Test Conditions/Comments
Residual Phase Noise @ 15.1 MHz (f
OUT
) with REFCLK
Multiplier Enabled 20×
@ 1 kHz Offset −127 dBc/Hz
@ 10 kHz Offset −136 dBc/Hz
@ 100 kHz Offset −139 dBc/Hz
@ 1 MHz Offset −138 dBc/Hz
Residual Phase Noise @ 40.1 MHz (f
OUT
) with REFCLK
Multiplier Enabled 20×
@ 1 kHz Offset −117 dBc/Hz
@ 10 kHz Offset −128 dBc/Hz
@ 100 kHz Offset −132 dBc/Hz
@ 1 MHz Offset −130 dBc/Hz
Residual Phase Noise @ 75.1 MHz (f
OUT
) with REFCLK
Multiplier Enabled 20×
@ 1 kHz Offset −110 dBc/Hz
@ 10 kHz Offset −121 dBc/Hz
@ 100 kHz Offset −125 dBc/Hz
@ 1 MHz Offset
−123
dBc/Hz
Residual Phase Noise @ 100.3 MHz (f
OUT
) with REFCLK
Multiplier Enabled 20×
@ 1 kHz Offset −107 dBc/Hz
@ 10 kHz Offset −119 dBc/Hz
@ 100 kHz Offset −121 dBc/Hz
@ 1 MHz Offset −119 dBc/Hz
SERIAL PORT TIMING CHARACTERISTICS
Maximum Frequency Serial Clock (SCLK) 200 MHz
Minimum SCLK Pulse Width Low (t
PWL
) 1.6 ns
Minimum SCLK Pulse Width High (t
PWH
) 2.2 ns
Minimum Data Setup Time (t
DS
) 2.2 ns
Minimum Data Hold Time 0 ns
Minimum
CS
Setup Time (t
PRE
)
1.0 ns
Minimum Data Valid Time for Read Operation 12 ns
MISCELLANEOUS TIMING CHARACTERISTICS
MASTER_RESET Minimum Pulse Width 1 Min pulse width = 1 sync clock period
I/O_UPDATE Minimum Pulse Width 1 Min pulse width = 1 sync clock period
Minimum Setup Time (I/O_UPDATE to SYNC_CLK) 4.8 ns Rising edge to rising edge
Minimum Hold Time (I/O_UPDATE to SYNC_CLK) 0 ns Rising edge to rising edge
Minimum Setup Time (Profile Inputs to SYNC_CLK) 5.4 ns
Minimum Hold Time (Profile Inputs to SYNC_CLK)
0
ns
Minimum Setup Time (SDIO Inputs to SYNC_CLK) 2.5 ns
Minimum Hold Time (SDIO Inputs to SYNC_CLK) 0 ns
Propagation Time Between REF_CLK and SYNC_CLK 2.25 3.5 5.5 ns
Profile Pin Toggle Rate 2 Sync
clocks
CMOS LOGIC INPUTS
V
IH
2.0 V
V
IL
0.8 V
Logic 1 Current
3
12
µA
Logic 0 Current −12 µA
Input Capacitance 2 pF
CMOS LOGIC OUTPUTS 1 mA load
V
OH
2.7
V
V
OL
0.4 V