Datasheet

Data Sheet AD9958
Rev. B | Page 15 of 44
Figure 25. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the Reference and SYNC_CLK
Figure 26. DDS Providing Stimulus for Acoustic Optical Tunable Filter
Figure 27. Agile Clock Source with Duty Cycle Control Using the Phase Offset Value in DDS to Change the DC Voltage to the Comparator
AD9958
(SLAVE 1)
AD9958
(MASTER)
CLOCK
SOURCE
AD9958
(SLAVE 2)
AD9958
(SLAVE 3)
REF_CLK
FPGA
DATA
SYNC_CLK
FPGA
DATA
SYNC_CLK
FPGA
DATA
SYNC_CLK
FPGA
DATA
SYNC_CLK
C1
S1
C2
S2
C3
S3
C4
S4
A1
A2
A4
A3
A_END
CENTRAL
CONTROL
AD9510
CLOCK DISTRIBUTOR
WITH
DELAY EQUALIZATION
SYNC_IN
SYNC_OUT
AD9510
SYNCHRONIZATION
DELAY EQUALIZATION
05252-027
ACOUSTIC OPTICAL
TUNABLE FILTER
OPTICAL FIBER CHANNEL
WITH MULTIPLE DISCRETE
WAVELENGTHS
OUTPUTS
INPUTS
SELECTABLE WAVELENGTH FROM EACH
CHANNEL VIA DDS TUNING AOTF
SPLITTER
WDM
SOURCE
WDM SIGNAL
CH0
CH1
CH0 CH1
CH0
CH1
AD9958
REFCLK
AMP
AMP
05252-028
CH0
AD9958
REFCLK
CH1
ADCMP563
–
+
05252-029