Datasheet

Data Sheet AD9957
Rev. C | Page 7 of 64
Parameter Test Conditions/Comments Min Typ Max Unit
CMOS LOGIC INPUTS
Voltage
Logic 1 2.0 V
Logic 0 0.8 V
Current
Logic 1 90 150 µA
Logic 0 90 150 µA
Input Capacitance 2 pF
XTAL_SEL INPUT
Logic 1 Voltage 1.25 V
Logic 0 Voltage 0.6 V
Input Capacitance 2 pF
CMOS LOGIC OUTPUTS 1 mA load
Voltage
Logic 1 2.8 V
Logic 0 0.4 V
POWER SUPPLY CURRENT
DVDD_I/O (3.3V) Pin Current Consumption QDUC mode 16 mA
DVDD (1.8V) Pin Current Consumption
QDUC mode
610
mA
AVDD (3.3V) Pin Current Consumption QDUC mode 28 mA
AVDD (1.8V) Pin Current Consumption QDUC mode 105 mA
POWER CONSUMPTION
Single Tone Mode 800 mW
Continuous Modulation 8× interpolation 1400 1800 mW
Inverse Sinc Filter Power Consumption 150 200 mW
Full Sleep Mode 12 40 mW
1
The system clock is limited to 750 MHz maximum in BFI mode.
2
The gain value for VCO range Setting 5 is measured at 1000 MHz.
3
Wake-up time refers to the recovery from analog power-down modes. The longest time required is for the Reference Clock Multiplier PLL to relock to the reference.
4
SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier and divider are not used, the
SYSCLK frequency is the same as the external reference clock frequency.