Datasheet

AD9957 Data Sheet
Rev. C | Page 60 of 64
PROFILE REGISTERS
There are eight consecutive serial I/O addresses (0x0E to 0x15)
dedicated to device profiles. All eight profile registers are either
single tone profiles or QDUC profiles depending on the device
operating mode specified by CFR1<25:24>. During operation,
the active profile register is determined via the external
PROFILE<2:0> pins.
Single tone profiles control: DDS frequency (32 bits), DDS
phase offset (16 bits), and DDS amplitude scaling (14 bits).
QDUC profiles control: DDS frequency (32 bits), DDS phase
offset (16 bits), output amplitude scaling (8 bits), CCI filter
interpolation factor, inverse CCI bypass, and spectral invert.
The QDUC profiles also selectively apply to the interpolating
DAC operating mode: only output scaling, CCI filter interpola-
tion factor, and inverse CCI bypass apply; all others (DDS
frequency, output amplitude scaling, and spectral invert) are
ignored.
Profile<7:0> Register—Single Tone
Address 0x0E to 0x15, eight bytes are assigned to this register.
Table 27. Bit Descriptions for Profile<7:0> Registers—Single Tone
Bit(s) Mnemonic Description
63:62 Open
61:48 Amplitude Scale Factor This 14-bit number controls the DDS output amplitude.
47:32 Phase Offset Word This 16-bit number controls the DDS phase offset.
31:0 Frequency Tuning Word This 32-bit number controls the DDS frequency.
Profile<7:0> Register—QDUC
Address 0x0E to 0x15, eight bytes are assigned to this register.
Table 28. Bit Descriptions for Profile<7:0> Registers—QDUC
Bit(s) Mnemonic Description
63:58 CC Interpolation Rate This 6-bit number is the rate interpolation factor for the CCI filter.
57 Spectral Invert 0: the modulator output takes the form: I(t) × cos(ct) – Q(t) × sin(ct).
1: the modulator output takes the form: I(t) × cos(ct) + Q(t) × sin(ct).
56 Inverse CCI Bypass 0: the inverse CCI filter is enabled.
1: the inverse CCI filter is bypassed.
55:48 Output Scale Factor This 8-bit number controls the output amplitude.
47:32 Phase Offset Word This 16-bit number controls the DDS phase offset.
31:0
Frequency Tuning Word
This 32-bit number controls the DDS frequency.
RAM Register
Address 0x16, four bytes are assigned to this register.
Table 29. Bit Descriptions for RAM Register
Bit(s) Mnemonic Description
31:0 RAM Word
The number of 32-bit words written to RAM is defined by the start and end address in
RAM Segment Register 0 or RAM Segment Register 1.
GPIO Configuration Register
Address 0x18, two bytes are assigned to this register.
Table 30. Bit Descriptions for GPIO Configuration Register
Bit(s) Mnemonic Description
15:0 GPIO Configuration See the General-Purpose I/O (GPIO) Port section for details.
GPIO Data Register
Address 0x19, two bytes are assigned to this register.
Table 31. Bit Descriptions for GPIO Data Register
Bits Mnemonic Description
15:0 GPIO Data
Read or write based on the contents of the GPIO Configuration register. See the
General-Purpose I/O (GPIO) Port section for details.