Datasheet

AD9957 Data Sheet
Rev. C | Page 6 of 64
Parameter Test Conditions/Comments Min Typ Max Unit
NOISE SPECTRAL DENSITY (NSD)
Single Tone
f
OUT
= 20.1 MHz −167 dBm/Hz
f
OUT
= 98.6 MHz −162 dBm/Hz
f
OUT
= 201.1 MHz
−157
dBm/Hz
f
OUT
= 397.8 MHz −151 dBm/Hz
TWO-TONE INTERMODULATION DISTORTION (IMD) I/Q rate = 62.5 MSPS; 16× interpolation
f
OUT
= 25 MHz
−82
dBc
f
OUT
= 50 MHz −78 dBc
f
OUT
= 100 MHz −73 dBc
MODULATOR CHARACTERISTICS
Input Data
Error Vector Magnitude 2.5 Msymbols/s, QPSK, 4× oversampled 0.53 %
270.8333 ksymbols/s, GMSK, 32×
oversampled
0.77 %
2.5 Msymbols/s, 256-QAM, 4×
oversampled
0.35 %
WCDMA—FDD (TM1), 3.84 MHz Bandwidth,
5 MHz Channel Spacing
Adjacent Channel Leakage Ratio (ACLR) IF = 143.88 MHz −78 dBc
Carrier Feedthrough
−78
dBc
SERIAL PORT TIMING CHARACTERISTICS
Maximum SCLK Frequency
70
Mbps
Minimum SCLK Pulse Width Low 4 ns
High 4 ns
Maximum SCLK Rise/Fall Time 2 ns
Minimum Data Setup Time to SCLK 5 ns
Minimum Data Hold Time to SCLK 0 ns
Maximum Data Valid Time in Read Mode 11 ns
I/O_UPDATE/PROFILE<2:0>/RT TIMING CHARACTERISTICS
Minimum Pulse Width
High
1
SYNC_CLK
cycle
Minimum Setup Time to SYNC_CLK 1.75 ns
Minimum Hold Time to SYNC_CLK 0 ns
I/Q INPUT TIMING CHARACTERISTICS
Maximum PDCLK Frequency 250 MHz
Minimum I/Q Data Setup Time to PDCLK 1.75 ns
Minimum I/Q Data Hold Time to PDCLK 0 ns
Minimum TxEnable Setup Time to PDCLK 1.75 ns
Minimum TxEnable Hold Time to PDCLK
0
ns
MISCELLANEOUS TIMING CHARACTERISTICS
Wake-Up Time
3
1
Fast Recovery Mode 8 SYSCLK cycles
4
Full Sleep Mode 150 μs
Minimum Reset Pulse Width High 5 SYSCLK cycles
4
DATA LATENCY (PIPELINE DELAY)
Data Latency Single Tone Mode
Frequency, Phase-to-DAC Output 79 SYSCLK cycles
4