Datasheet

AD9957 Data Sheet
Rev. C | Page 58 of 64
Control Function Register 3 (CFR3)
Address 0x02, four bytes are assigned to this register.
Table 20. Bit Descriptions for CFR3 Register
Bit (s) Mnemonic Description
31:30 Open
29:28
DRV0
Controls REFCLK_OUT pin (see Table 6 for details); default is 01b.
27 Open
26:24 VCO SEL Selects frequency band of the VCO in the REFCLK PLL (see Table 7 for details); default is 111b.
23:22 Open
21:19 I
CP
Selects the charge pump current in the REFCLK PLL (see Table 8 for details); default is 111b.
18:16 Open
15
REFCLK Input Divider
Bypass
0: input divider is selected (default).
1: input divider is bypassed.
14
REFCLK Input Divider
ResetB
0: input divider is reset.
1: input divider operates normally (default).
13:9 Open
8
PLL Enable
0: REFCLK PLL bypassed (default).
1: REFCLK PLL enabled.
7:1 N This 7-bit number is divide modulus of the REFCLK PLL feedback divider; default is 0000000b.
0 Open
Auxiliary DAC Control Register
Address 0x03, four bytes are assigned to this register.
Table 21. Bit Descriptions for Auxiliary DAC Control Register
Bit(s) Mnemonic Description
31:8 Open
7:0 FSC
This 8-bit number controls the full-scale output current of the main DAC (see the Auxiliary DAC section);
default is 0xFF.
I/O Update Rate Register
Address 0x04, four bytes are assigned to this register. This register is effective without the need for an I/O update.
Table 22. Bit Descriptions for I/O Update Rate Register5
Bit(s) Mnemonic Description
31:0 I/O Update Rate
Ineffective unless CFR2<23> = 1. This 32-bit number controls the automatic I/O update rate (see the
Automatic I/O Update section); default is 0xFFFFFFFF.
RAM Segment Register 0
Address 0x05, six bytes are assigned to this register. This register is effective without the need for an I/O update. This register is only
active if CFR1<31> = 1 and there is a Logic 0-to-Logic 1 transition on the RT pin.
Table 23. Bit Descriptions for RAM Segment Register 0
Bit(s) Mnemonic Description
47:32
RAM Address Step
Rate 0
This 16-bit number controls the rate at which the RAM state machine steps through the specified RAM
address range.
31:22 RAM End Address 0 This 10-bit number identifies the ending address for the RAM state machine.
21:16 Open
15:6 RAM Start Address 0 This 10-bit number identifies the starting address for the RAM state machine.
5:3 Open
2:0 RAM Playback Mode 0 This 3-bit number identifies the playback mode for the RAM state machine (see Table 5).