Datasheet

AD9957 Data Sheet
Rev. C | Page 36 of 64
PLL CHARGE PUMP
The charge pump current (I
CP
) is programmable to provide the
user with additional flexibility to optimize the PLL performance.
Table 8 lists the bit settings vs. the nominal charge pump
current.
Table 8. PLL Charge Pump Current
I
CP
(CFR3<21:19>) Charge Pump Current, I
CP
(μA)
000 212
001 237
010 262
011
287
100 312
101 337
110 363
111 387
EXTERNAL PLL LOOP FILTER COMPONENTS
The PLL_LOOP_FILTER pin provides a connection interface to
attach the external loop filter components. The ability to use
custom loop filter components gives the user more flexibility to
optimize the PLL performance. The PLL and external loop filter
components are shown in Figure 52.
PFD CP
PLL_LOOP_FILTER
VCO
÷N
PLL OUT
PLL IN
AVDD
REFCLK PLL
2
R1
C1
C2
06384-030
Figure 52. REFCLK PLL External Loop Filter
In the prevailing literature, this configuration yields a third-
order, Type II PLL. To calculate the loop filter component
values, begin with the feedback divider value (N), the gain of
the phase detector (K
D
), and the gain of the VCO (K
V
) based on
the programmed VCO SEL bit settings (see Table 1 for K
V
). The
loop filter component values depend on the desired open-loop
bandwidth (f
OL
) and phase margin (φ), as follows:
( )








+=
φKK
Nfπ
R1
VD
OL
sin
1
1
(7)
( )
( )
2
2
tan
OL
VD
fN
KK
C1
π
φ
=
(8)
( )
( )








−
=
φ
φ
fπN
KK
C2
OL
VD
cos
sin1
)2(
2
(9)
where:
K
D
equals the programmed value of I
CP
.
K
V
is taken from Table 1.
Ensure that proper units are used for the variables in Equation 7
through Equation 9. I
CP
must be in amps, not μA as appears in
Table 8; K
V
must be in Hz/V, not MHz/V as listed in Table 1; the
loop bandwidth (f
OL
) must be in Hz; the phase margin (φ) must
be in radians.
For example, suppose the PLL is programmed such that
I
CP
= 287 μA, K
V
= 625 MHz/V, and N = 25. If the desired loop
bandwidth and phase margin are 50 kHz and 45°, respectively,
the loop filter component values are R1 = 52.85 Ω, C1 = 145.4 nF,
and C2 = 30.11 nF.
PLL LOCK INDICATION
When the PLL is in use, the PLL_LOCK pin provides an active
high indication that the PLL has locked to the REFCLK input
signal. When the PLL is bypassed, the PLL_LOCK pin defaults
to Logic 0.