Datasheet
AD9957 Data Sheet
Rev. C | Page 30 of 64
RAM Bidirectional Ramp Mode
This mode is unique in that the RAM segment playback mode
word of both RAM segment registers must be programmed for
RAM bidirectional ramp mode.
In bidirectional ramp mode, upon assertion of an I/O update,
the RAM readies for playback operation using the parameters
programmed into RAM Segment Register 0. The data is deliv-
ered at the appropriate rate and to the destination as specified
by the RAM playback destination bit.
The playback rate is governed by the timer that is internal to the
RAM state machine, and its period (Δt) is determined by the
state of the RAM playback destination bit as detailed in the
RAM Playback Operation section.
Playback begins upon a 0 to 1 logic transition on the RT pin.
This instructs the state machine to increment through the
address range specified in RAM Segment Register 0 starting
with the start address. As long as the RT pin remains Logic 1,
the state machine continues to play back the RAM data until it
reaches the end address, at which point the state machine halts.
A Logic 1 to Logic 0 transition on the RT pin instructs the state
machine to switch to RAM Segment Register 1 and to decrement
through the address range starting with the end address. As
long as the RT pin remains Logic 0, the state machine continues
to play back the RAM data until it reaches the start address, at
which point the state machine halts.
It is important to note that RAM Segment Register 1 is played
back in reverse order for bidirectional ramp mode. This must
be kept in mind when the RAM contents are loaded via the
serial I/O port when bidirectional ramp mode is the intended
playback mode.
A graphic representation of the bidirectional ramp mode
appears in Figure 44. It demonstrates the action of the state
machine in response to the RT pin. If the RT pin changes states
before the state machine reaches the programmed start or end
address, the internal timer is restarted and the direction of the
address counter reversed.
1 2 3 4 5 6 7 8
06384-024
1
RAM SEGMENT
0
1 0 1 0
Δ
t
Δt
Δt
Δt
Δt
START ADDRESS NUMBER 1
START ADDRESS NUMBER 0
END ADDRESS NUMBER 1
END ADDRESS
NUMBER 0
RAM
ADDRESS
RAM
ADDRESS
RT
PIN
1 PDCLK CYCLE
OR
M DDS CLOCK CYCLES
I/O_UPDATE
Figure 44. Bidirectional Ramp Timing Diagram