Datasheet

AD9957 Data Sheet
Rev. C | Page 2 of 64
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 4
Specifications ..................................................................................... 5
Electrical Specifications ............................................................... 5
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 12
Modes of Operation ....................................................................... 16
Overview ...................................................................................... 16
Quadrature Modulation Mode ................................................. 17
BlackFin Interface (BFI) Mode ................................................. 18
Interpolating DAC Mode .......................................................... 19
Single Tone Mode ....................................................................... 20
Signal Processing ............................................................................ 21
Parallel Data Clock (PDCLK) ................................................... 21
Transmit Enable Pin (TxEnable) .............................................. 21
Input Data Assembler ................................................................ 22
Inverse CCI Filter ....................................................................... 23
Fixed Interpolator (4×) .............................................................. 23
Programmable Interpolating Filter .......................................... 24
QDUC Mode ........................................................................... 24
BFI Mode ................................................................................. 24
Quadrature Modulator .............................................................. 25
DDS Core ..................................................................................... 25
Inverse Sinc Filter ....................................................................... 25
Output Scale Factor (OSF) ........................................................ 26
14-Bit DAC .................................................................................. 26
Auxiliary DAC ........................................................................ 26
RAM Control .................................................................................. 27
RAM Overview ........................................................................... 27
RAM Segment Registers ............................................................ 27
RAM State Machine ................................................................... 27
RAM Trigger (RT) Pin ............................................................... 27
Load/Retrieve RAM Operation ................................................ 28
RAM Playback Operation ......................................................... 28
Overview of RAM Playback Modes ......................................... 29
RAM Ramp-Up Mode ........................................................... 29
RAM Bidirectional Ramp Mode .......................................... 30
RAM Continuous Bidirectional Ramp Mode .................... 32
RAM Continuous Recirculate Mode ................................... 33
Clock Input (REF_CLK) ................................................................ 34
REFCLK Overview ..................................................................... 34
Crystal Driven REF_CLK ......................................................... 34
Direct Driven REF_CLK ........................................................... 34
Phase-Locked Loop (PLL) Multiplier ...................................... 35
PLL Charge Pump ...................................................................... 36
External PLL Loop Filter Components ................................... 36
PLL Lock Indication .................................................................. 36
Additional Features ........................................................................ 37
Output Shift Keying (OSK) ....................................................... 37
Manual OSK ............................................................................ 37
Automatic OSK ....................................................................... 37
Profiles ......................................................................................... 38
I/O_UPDATE Pin ...................................................................... 38
Automatic I/O Update ............................................................... 38
Power-Down Control ................................................................ 39
General-Purpose I/O (GPIO) Port .......................................... 39
Synchronization of Multiple Devices ........................................... 40
Overview ..................................................................................... 40
Clock Generator ......................................................................... 40