Datasheet
Data Sheet AD9957
Rev. C | Page 19 of 64
INTERPOLATING DAC MODE
A block diagram of the AD9957 operating in interpolating DAC
mode is shown in Figure 28; grayed items are inactive. In this
mode, the Q data path, DDS, and modulator are all disabled; only
the I data path is active.
As in quadrature modulation mode, the PDCLK pin functions
as a clock, synchronizing the input of data to the AD9957.
No modulation takes place in the interpolating DAC mode;
therefore, the spectrum of the data supplied at the parallel port
remains at baseband. However, a sample rate conversion takes
place based on the programmed interpolation rate. The inter-
polation hardware processes the signal, effectively performing
an oversample with a zero-stuffing operation. The original
input spectrum remains intact and the images that otherwise
would occur from the sample rate conversion process are
suppressed by the interpolation signal chain.
06384-008
PDCLK
I/Q IN
EXT_PWR_DWN
DAC_RSET
IOUT
IOUT
TxENABLE
DAC GAIN
θ
INVERSE
SINC
FILTER
CLOCK
FTW
PW
8
SYSCLK
PLL
÷2
CLOCK MODE
REF_CLK
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND CONTROL
AD9957
ω
cos (ωt+θ)
sin (ωt+θ)
SYNC_OUT
SYNC_IN
PLL_LOCK
PLL_LOOP_FILTER
MASTER_RESET
2
2
DDS
AUX
DAC
8-BIT
POWER
DOWN
CONTROL
18
DATA ASSEMBLER AND FORMATTER
I
Q
IS
QS
BLACKFIN INTERFACE
18
18
16
16
HALF-BAND
FILTERS (4×)
INVERSE
CCI
CCI
(1× TO 63×)
HALF-BAND
FILTERS (4×)
INVERSE
CCI
CCI
(1× TO 63×)
OSK
INTERNAL CLOCK TIMING AND CONTROL
DAC
14-BIT
FTW
PW
OSK
RT
RAM
PROFILE
SERIAL I/O
PORT
I/O_UPDATE
PROGRAMMING
REGISTERS
3
I Q IS QS
OUTPUT
SCALE
FACTOR
CCI_OVFL
SDIO
CS
I/O_RESET
SCLK
SDO
Figure 28. Interpolating DAC Mode