Datasheet

Data Sheet AD9957
Rev. C | Page 17 of 64
QUADRATURE MODULATION MODE
A block diagram of the AD9957 operating in QDUC mode is
shown in Figure 26; grayed items are inactive. The parallel input
accepts 18-bit I- and Q-words in time-interleaved fashion. That
is, an 18-bit I-word is followed by an 18-bit Q-word, then the
next 18-bit I-word, and so on. One 18-bit I-word and one 18-bit
Q-word together comprise one internal sample. The data assem-
bler and formatter de-interleave the I- and Q-words so that each
sample propagates along the internal data pathway in parallel
fashion. Both I and Q data paths are active; the parallel data
clock (PDCLK) serves to synchronize the input of I/Q data to
the AD9957.
The PROFILE and I/O_UPDATE pins are also synchronous to
the PDCLK.
The DDS core provides a quadrature (sine and cosine) local
oscillator signal to the quadrature modulator, where the
interpolated I and Q samples are multiplied by the respective
phase of the carrier and summed together, producing a
quadrature modulated data stream. This data stream is routed
through the inverse sinc filter (optionally), and the output
scaling multiplier. Then it is applied to the 14-bit DAC to
produce the quadrature modulated analog output signal.
06384-006
PDCLK
I/Q IN
EXT_PWR_DWN
DAC_RSET
IOUT
IOUT
TxENABLE
DAC GAIN
OUTPUT
SCALE
FACTOR
θ
INVERSE
SINC
FILTER
CLOCK
FTW
PW
8
SYSCLK
PLL
÷2
CLOCK MODE
REF_CLK
REF_CLK
REFCLK_OUT
XTAL_SE
L
AD9957
ω
cos (ωt+θ)
sin (ωt+θ)
SYNC_OUT
SYNC_IN
PLL_LOCK
PLL_LOOP_FILTER
MASTER_RESET
2
2
OSK
DDS
AUX
DAC
8-BIT
POWER
DOWN
CONTROL
18
DATA ASSEMBLER AND FORMATTER
I
Q
IS
QS
BLACKFIN INTERFACE
18
18
16
16
INVERSE
CCI
INVERSE
CCI
OSK
INTERNAL CLOCK TIMING AND CONTROL
DAC
14-BIT
CCI_OVFL
FTW
PW
PARALLEL DATA
TIMING AND CONTROL
RT
RAM
PROFILE
SERIAL I/O
PORT
I/O_UPDATE
PROGRAMMING
REGISTERS
3
I Q IS QS
HALF-BAND
FILTERS (4×)
CCI
(1× TO 63×)
HALF-BAND
FILTERS (4×)
CCI
(1× TO 63×)
SDIO
CS
I/O_RESET
SCLK
SDO
Figure 26. Quadrature Modulation Mode