Datasheet

AD9956
Rev. A | Page 6 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
160 MHz Analog Out (±1 MHz) −81 dBc
160 MHz Analog Out (±250 kHz) −83 dBc
160 MHz Analog Out (±50 kHz) −85 dBc
DAC Residual Phase Noise
19.7 MHz F
OUT
@ 10 Hz Offset 125 dBc/Hz
@ 100 Hz Offset 135 dBc/Hz
@ 1 kHz Offset 143 dBc/Hz
@ 10 kHz Offset 152 dBc/Hz
@ 100 kHz Offset 158 dBc/Hz
>1 MHz Offset 163 dBc/Hz
51.84 MHz F
OUT
@ 10 Hz Offset 119 dBc/Hz
@ 100 Hz Offset 125 dBc/Hz
@ 1 kHz Offset 132 dBc/Hz
@ 10 kHz Offset 142 dBc/Hz
@ 100 kHz Offset 150 dBc/Hz
>1 MHz Offset 155 dBc/Hz
105.3 MHz Analog Out
@ 10 Hz Offset 105 dBc/Hz
@ 100 Hz Offset 115 dBc/Hz
@ 1 kHz Offset 122 dBc/Hz
@ 10 kHz Offset 131 dBc/Hz
@ 100 kHz Offset 139 dBc/Hz
>1 MHz Offset 142 dBc/Hz
155.52 MHz Analog Out
@ 10 Hz Offset 105 dBc/Hz
@ 100 Hz Offset 110 dBc/Hz
@ 1 kHz Offset 119 dBc/Hz
@ 10 kHz Offset 127 dBc/Hz
@ 100 kHz Offset 135 dBc/Hz
>1 MHz Offset 142 dBc/Hz
CRYSTAL OSCILLATOR (ON PLLREF INPUT)
Operating Range 20 25 30 MHz
Residual Phase Noise (@ 25 MHz)
@ 10 Hz Offset 95 dBc/Hz
@ 100 Hz Offset 120 dBc/Hz
@ 1 kHz Offset 137 dBc/Hz
@ 10 kHz Offset 156 dBc/Hz
@ 100 kHz Offset 164 dBc/Hz
>1 MHz Offset 170 dBc/Hz
DIGITAL TIMING SPECIFICATIONS
CS
to SCLK Setup Time TPRE
6 ns
Period of SCLK (Write Speed) TSCLKW 40 ns
Period of SCLK (Read Speed) TSCLKR 400 ns
Serial Data Setup Time TDSU 6.5 ns
Serial Data Hold Time TDHLD 0 ns
TDV Data Valid Time TDV 40 ns
I/O Update to SYNC_CLK Setup Time TUD 7 ns
PS<2:0> to SYNC_CLK Setup Time TPS 7 ns