Datasheet

AD9956
Rev. A | Page 4 of 32
SPECIFICATIONS
AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± 5% (@ T
A
= 25°C) DAC_R
SET
= 3.92 kΩ, CP_R
SET
= 3.09 kΩ,
DRV_R
SET
= 4.02 kΩ, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
RF DIVIDER (REFCLK ) INPUT SECTION (÷R)
RF Divider Input Range 1 2700 MHz
DDS SYSCLK not to exceed
400 MSPS
Input Capacitance (DC) 3 pF
Input Impedance (DC) 1500 Ω
Input Duty Cycle 42 50 58 %
Input Power/Sensitivity −10 +4 dBm Single-ended, into a 50 Ω load
1
Input Voltage Level 350 1000 mV p-p
PHASE FREQUENCY DETECTOR/CHARGE PUMP
PLLREF Input
Input Frequency
2
÷M Set to Divide by at Least 4 655 MHz
÷M Bypassed 200 MHz
Input Voltage Levels 200 450 600 mV p-p
Input Capacitance 10 pF
Input Resistance 1500 Ω
PLLOSC Input
Input Frequency
÷N Set to Divide by at Least 4 655 MHz
÷N Bypassed 200 MHz
Input Voltage Levels 200 450 600 mV p-p
Input Capacitance 10 pF
Input Resistance 1500 Ω
Charge Pump Source/Sink Maximum Current 4 mA
Charge Pump Source/Sink Accuracy −15 +5 %
Charge Pump Source/Sink Matching −5 +5 %
Charge Pump Output Compliance Range
3
0.5 CP_VDD − 0.5 V
PLL_LOCK Drive Strength 2 mA
PHASE FREQUENCY DETECTOR NOISE FLOOR
@ 50 kHz PFD Frequency 149 dBc/Hz
@ 2 MHz PFD Frequency 133 dBc/Hz
@ 100 MHz PFD Frequency 116 dBc/Hz
@ 200 MHz PFD Frequency 113 dBc/Hz
CML OUTPUT DRIVER (DRV)
Differential Output Voltage Swing
4
720 mV 50 Ω load to supply, both lines
Maximum Toggle Rate 655 MHz
Common-Mode Output Voltage 1.75 V
Output Duty Cycle 42 50 58 %
Output Current
Continuous
5
7.2 mA
Rising Edge Surge 20.9 mA
Falling Edge Surge 13.5 mA
Output Rise Time 250 ps 100 Ω terminated, 5 pF load