Datasheet

AD9956

Rev. A | Page 19 of 32

CML DRIVER

For clocking applications, an on-chip current mode logic

(CML) driver is included. This CML driver generates very low

jitter clock edges. The outputs of the CML driver are current

outputs and drives PECL levels when terminated into a 100 Ω

load. The base output current of the driver is programmed by

attaching a resistor from the DRV_RSET pin to ground (nomi-

nally 4.02 kΩ for a continuous current of 7.2 mA). An optional

on-chip current programming resistor is enabled by setting a bit

in the control register. The rising edge and falling edge slew

rates are independently programmable to help control over-

shoot and ringing through the application of surge current

during rising edge transitions and falling edge transitions (see

Figure 27). There is a default surge current of 7.6 mA on the

rising edge and 4.05 mA on the falling edge. Bits in the control

current, as well disable the default surge current (see the

Control Function Register Descriptions section for details). The

CML driver can be driven by the

• RF divider input

• RF divider output

• PLLOSC input

I(t)

~250ps~250ps

RISING EDGE SURGE

CONTINUOUS

FALLING EDGE SURGE

CONTINUOUS

04806-0-002

Figure 27. Rising Edge and Falling Edge Surge Current Output of the

CML Clock Driver, as Opposed to the Steady State Continuous Current