Datasheet

AD9954
Rev. B | Page 9 of 40
Pin No. Mnemonic I/O Description
31
COMP_IN
I Comparator Complementary Input.
35 PWRDWNCTL I Input Pin Used as an External Power-Down Control (see Table 9 for details).
36 RESET I
Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9954 to the default
state, as described in the right-hand column of Table 12, which is the I/O port register map.
37 IOSYNC I
Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O
operation is immediately terminated, enabling a new I/O operation to commence once
IOSYNC is returned low. If unused, ground this pin; do not allow this pin to float.
38 SDO O See Serial Interface Port Pin Description section for details.
39
CS
I See Serial Interface Port Pin Description section for details.
40 SCLK I See Serial Interface Port Pin Description section for details.
41 SDIO I/O See Serial Interface Port Pin Description section for details.
43 DVDD_I/O I Digital Power Supply. This pin is for I/O cells only, 3.3 V.
44 SYNC_IN I
Input Signal Used to Synchronize Multiple AD9954s. This input is connected to the SYNC_CLK
output of a master AD9954.
45 SYNC_CLK O Clock Output Pin that Serves as a Synchronizer for External Hardware.
46 OSK I
Input Pin Used to Control the Direction of the Shaped On-Off Keying Function When Programmed
for Operation. OSK is synchronous to the SYNC_CLK pin. When OSK is disabled, this pin should
be tied to DGND.
47, 48 PS0, PS1 I
Input Pins Used to Select One of the Internal Phase/Frequency Profiles. PS1 and PS0 are
synchronous to the SYNC_CLK pin. Change on these pins triggers a transfer of the contents of
the chosen internal buffer memory to the I/O registers (sends an internal I/O UPDATE).
<49> AGND I
The Exposed Paddle on the Bottom of the Package. It is a ground connection for the DAC and
must be attached to AGND in any board layout.