Datasheet
AD9954
Rev. B | Page 8 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CS
03374-002
31
34
DVDD
33
DGND
32
AGND
29
AVDD
30
COMP_IN
COMP_IN
35
PWRDWNCTL
36
RESET
28
COMP_OUT
27
AVDD
26
AGND
25
AVDD
PIN 1
AD9954
TOP VIEW
(Not to Scale)
13
AVDD
14
AGND
15
AGND
16
AVDD
17
AGND
18
AVDD
19
AVDD
20
IOUT
21
IOUT
22
AGND
23
DACBP
24
DAC_
R
SET
48
PS1
47
PS0
46
OSK
45
SYNC_CLK
44
SYNC_IN
43
DVDD_I/O
42
DGND
41
SDIO
40
SCLK
39 38
SDO
37
IOSYNC
2
DVDD
3
DGND
4
AVDD
7
AGND
6
AVDD
5
AGND
1
I/O UPDATE
8
OSC/REFCLK
9
OSC/REFCLK
10
CRYSTAL OUT
12
LOOP_FILTER
11
CLKMODESELECT
Figure 4. Pin Configuration
Note that the exposed paddle on the bottom of the package forms an electrical connection for the DAC and must be attached to
analog ground. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or 3.3 V. The DVDD pins (Pin 2 and Pin 34) must be
powered to 1.8 V.
Table 3. Pin Function Descriptions
Pin No. Mnemonic I/O Description
1 I/O UPDATE I
The rising edge transfers the contents of the internal buffer memory to the I/O registers.
See Synchronization—Register Updates (I/O UPDATE) section for details.
2, 34 DVDD I Digital Power Supply Pins (1.8 V).
3, 33, 42 DGND I Digital Power Ground Pins.
4, 6, 13, 16,
18, 19, 25,
27, 29
AVDD I Analog Power Supply Pins (1.8 V).
5, 7, 14, 15,
17, 22, 26,
32
AGND I Analog Power Ground Pins.
8
OSC
/REFCLK
I
Oscillator Input/Complementary Reference Clock. When the REFCLK port is operated in
single-ended mode, REFCLK
should be decoupled to AVDD with a 0.1 µF capacitor.
9 OSC/REFCLK I Oscillator Input/Reference Clock. See Table 5 for details on the OSC/REFCLK operation.
10 CRYSTAL OUT O Output of the Oscillator Section.
11 CLKMODESELECT I
Control Pin for the Oscillator Section (1.8 V logic only). See REFCLK Input section for detailed
instructions.
12 LOOP_FILTER I
This pin provides the connection for the external zero compensation network of the REFCLK
multiplier’s PLL loop filter. The network varies based on the multiplication value in the PLL loop.
See Table 4 for details.
20
IOUT
O Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND.
21 IOUT O DAC Output. Should be biased through a resistor to AVDD, not AGND.
23 DACBP I DAC Band Gap Decoupling Pin. A 0.1 F capacitor to AGND is recommended.
24 DAC_R
SET
I
A resistor (3.92 kΩ nominal) connected from AGND to DAC_R
SET
establishes the reference
current for the DAC. See equation in DAC Output section.
28 COMP_OUT O Comparator Output.
30 COMP_IN I Comparator Input.