Datasheet

AD9954
Rev. B | Page 5 of 40
Parameter Temp
Test
Level Min Typ Max Unit
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance 25°C V 3 pF
Input Resistance 25°C IV 500 kΩ
Input Current 25°C I ±12 µA
Hysteresis 25°C IV 30 45 mV
COMPARATOR OUTPUT CHARACTERISTICS
Logic 1 Voltage, High-Z Load Full VI 1.6 V
Logic 0 Voltage, High-Z Load Full VI 0.4 V
Propagation Delay 25°C IV 3 ns
Output Duty-Cycle Error 25°C IV ±5 %
Rise/Fall Time, 5 pF Load 25°C IV 1 ns
Toggle Rate, High-Z Load 25°C IV 200 MHz
Output Jitter
1
25°C IV 1 ps rms
COMPARATOR NARROW-BAND SFDR
10 MHz to 160 MHz F
OUT
Measured over a 1 MHz BW 25°C V 80 dBc
Measured over a 250 kHz BW 25°C V 85 dBc
Measured over a 50 kHz BW 25°C V 90 dBc
Measured over a 10 Hz BW 25°C V 95 dBc
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency Full IV 25 Mbps
Minimum Clock Pulse Width Low Full IV 7 ns
Minimum Clock Pulse Width High Full IV 7 ns
Maximum Clock Rise/Fall Time Full IV 2 ns
Minimum Data Setup Time DVDD_I/O = 3.3 V Full IV 3 ns
Minimum Data Setup Time DVDD_I/O = 1.8 V Full IV 5 ns
Minimum Data Hold Time Full IV 0 ns
Maximum Data Valid Time Full IV 25 ns
Wake-Up Time
2
Full I
V
1 ms
Minimum Reset Pulse Width High Full IV 5
SYSCLK
cycles
3
I/O UPDATE, PS0, PS1 to SYNC_CLK Setup Time, DVDD_I/O = 3.3 V Full I 4 ns
I/O UPDATE, PS0, PS1 to SYNC_CLK Setup Time, DVDD_I/O = 1.8 V Full I 6 ns
I/O UPDATE, PS0, PS1 to SYNC_CLK Hold Time Full I 0 ns
Latency
I/O UPDATE to Frequency Change Prop Delay 25°C IV 24
SYSCLK
cycles
I/O UPDATE to Phase Offset Change Prop Delay 25°C IV 24
SYSCLK
cycles
I/O UPDATE to Amplitude Change Prop Delay 25°C IV 16
SYSCLK
cycles
PS0, PS1 to RAM Driven Frequency Change Prop Delay 25°C IV 28
SYSCLK
cycles
PS0, PS1 to RAM Driven Phase Change Prop Delay 25°C IV 28
SYSCLK
cycles
PS0 to Linear Frequency Sweep Prop Delay 25°C IV 28
SYSCLK
cycles