Datasheet
AD9954
Rev. B | Page 37 of 40
C21
0.1µF
C20
0.1µF
C19
0.1µF
C18
0.1µF
C23
0.1µF
C16
0.1µF
C15
0.1µF
C14
0.1µF
C13
0.1µF
GND
AVDD
C24
0.1µF
C22
0.1µF
GND
DVDD
C17
0.1µF
GND
DVDD_I/O
RESET_DUT2
PWRDWNCTRL_DUT2
DVDD
GND
GND
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
3
1
5
4
5
6
7
8
9
10
11
12
4
AVDD
5
6
3
2
1
AVDD
AVDD
AVDD
GND
RESET
PWRDWNCTL
DVDD
DGND
AGND
AD9954
U8
DUT 2
COMP_IN
COMP_IN
AVDD
COMP_OUT_DUT2
J9
COMP_OUT
AVDD
AVDD
AGND
FUD_DUT2
DVDD
GND
AVDD
GND
GND
AVDD
XTAL_OUT
CLKMODESEL_DUT2
I/O UPDATE
DVDD
DGND
AVDD
AGND
AGND
AVDD
OSC/REFCLK
OSC/REFCLK
CRYSTAL OUT
CLKMODESELECT
LOOP_FILTER
J14
W3
4
12
3
48
47
46
45
44
43
42
41
40
39
38
37
PS1
PS0
OSK
SYNC_CLK
SYNC_IN
DVDD_I/O
DGND
SDIO
SCLK
CS
IOSYNC
SDO
PS1_DUT2
PS0_DUT2
OSK_DUT2
SYNCMULTI_DUT1
SYNCMULTI_DUT
2
DVDD_I/O
GND
SDIO
SCLK
CSB_DUT2
I/O_SYNC_DUT2
SDO
13
14
15
16
17
18
19
20
21
22
23
24
AVDD
AGND
AGND
AVDD
AGND
AVDD
AVDD
AVDD
AVDD
AVDD
GND
GND
AVDD
GND
GND
AVDD
AVDD
IOUT
IOUT
AGND
DAC_R
SET
DACBP
GND
NOTE 2
NOTE 1
NOTE 3
AVDD
GND
COMP_IN
J10
GND AVDD
FILTER_IN_DUT2
COMP_IN
J11
AVDD
GND
J12
FILTER_IOUT_DUT2
J6
REF_CLK_DUT2
BALUN
T4
J7
CRYSTAL OUT
DUT2
GND
AVDD
XTAL_OUT
XTAL_DUT2
NOTES
1. THE FULL-SCALE DAC OUTPUT CURRENT IS CONTROLLED BY MEANS OF AN EXTERNAL
RESISTANCE (R
SET
) CONNECTED BETWEEN THE DAC_R
SET
PIN AND GROUND. RESISTOR
VALUES FOR FULL-SCALE CURRENTS ARE: 3.92kΩ = 10mA, 5.23kΩ = 7.5mA, 7.87kΩ = 5.0mA,
15.8kΩ = 2.5mA.
2. C58 IS USED FOR A SIMULATED CAPACITANCE LOAD FOR THE COMPARATOR OUT. THE
CAPACITANCE VALUE SHOULD NOT EXCEED 10pF.
3. FOR CRYSTAL OUT CLOCK OPERATION REMOVE T4, TERMINATE THE OSC/REFCLK TO
EITHER AVDD (R30) OR GND (R31) AND SOLDER R21 IN PLACE. DO NOT USE R30 OR R31
SIMULTANEOUSLY.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P50
P49
P48
P47
P46
P45
P44
P43
P42
P41
P40
P39
P38
P37
P36
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
RESET_DUT1
CLKMODESEL_DUT1
PWRDWNCTRL_DUT1
I/O_SYNC_DUT1
FUD_DUT1
OSK_DUT1
PS1_DUT1
PS0_DUT1
CS_DUT2
RESET_DUT2
CLKMODESEL_DUT2
PWRDWNCTRL_DUT2
I/O_SYNC_DUT2
FUD_DUT2
OSK_DUT2
PS1_DUT2
PS0_DUT2
RB_ENABLE
SDIO
SDO
SCLK
GND
U13
CS_DUT1
C65
0.1µF
C66
0.1µF
C58
SEE NOTE 2
R24
10kΩ
R11
3.3kΩ
R25
10kΩ
R2
3.3kΩ
C62
1µF
C61
0.01µF
C64
0.1µF
C63
0.1µF
R15
3.92kΩ
R9
25Ω
R22
25Ω
R16
243Ω
R21
0Ω
R30
0Ω
R31
0Ω
R18
50Ω
C59
13pF
C53
13pF
L10
39nH
C57
27pF
C60
6.8pF
L12
56nH
C56
33pF
C55
22pF
C54
2.2pF
L11
68nH
03374-034
Figure 36. Evaluation Board Channel 2