Datasheet
AD9954
Rev. B | Page 26 of 40
Table 12. Register Map—When Linear Sweep Enable Bit Is False (CFR1<21> = 0)
Note that the RAM Enable Bit CFR1<31> only activates the RAM itself, not the RAM segment control words.
Register
Name
(Serial
Address)
Bit
Range
(MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value Or
Profile
Control
Function
Register
No.1
(CFR1)
(0x00)
<7:0>
Digital
Power-
Down
Comp
Power-
Down
DAC
Power-
Down
Clock
Input
Power-
Down
External
Power-
Down
Mode
Linear
Sweep
No-
Dwell
SYNC_CLK
Disable
Not
Used
0x00
<15:8>
SRR Load
Enable
AutoClr
Freq
Accum
AutoClr
Phase
Accum
Sine/
Cosine
Select
Clear
Freq
Accum
Clear
Phase
Accum
SDIO
Input
Only
LSB First 0x00
<23:16>
Automatic
Sync
Enable
Software
Manual
Sync
Linear
Sweep
Enable
Not Used
Not
Used
Not Used Not Used
Not
Used
0x00
<31:24>
RAM
Enable
RAM
Destination
Internal Profile Control<2:0>
Load ARR
Control
OSK
Enable
Auto
OSK
Enable
0x00
Control
Function
Register
No. 2
(CFR2)
(0x01)
<7:0> REFCLK Multiplier
VCO
Range
Charge Pump
Current<1:0>
0x00
<15:8> Not Used
High
Speed
Sync
Enable
Hardware
Manual
Sync
Enable
XTAL
OUT
Enable
Not
Used
0x00
<23:16> Not Used 0x18
Amplitude
Scale
Factor (ASF)
(0x02)
<7:0> Amplitude Scale Factor Register<7:0> 0x00
<15:8>
Auto Ramp Rate
Speed Control<1:0>
Amplitude Scale Factor Register<13:8> 0x00
Amplitude
Ramp Rate
(ARR)
(0x03)
<7:0> Amplitude Ramp Rate Register<7:0> 0x00
Frequency
Tuning
Word
(FTW0)
(0x04)
<7:0> Frequency Tuning Word No. 0<7:0> 0x00
<15:8> Frequency Tuning Word No. 0<15:8> 0x00
<23:16> Frequency Tuning Word No. 0<23:16> 0x00
<31:24> Frequency Tuning Word No. 0<31:24> 0x00
Phase
Offset Word
(POW0)
(0x05)
<7:0> Phase Offset Word No. 0<7:0> 0x00
<15:8> Not Used<1:0> Phase Offset Word No. 0<13:8> 0x00
Frequency
Tuning
Word
(FTW1)
(0x06)
<7:0> Frequency Tuning Word No. 1<7:0> 0x00
<15:8> Frequency Tuning Word No. 1<15:8> 0x00
<23:16> Frequency Tuning Word No. 1<23:16> 0x00
<31:24> Frequency Tuning Word No. 1<31:24> 0x00
Profile 0
RAM
Segment
Control
Word No. 0
(RSCW0)
(0x07)
<7:0>
RAM Segment 0 Mode
Control<2:0>
No-Dwell
Active
RAM Segment 0 Beginning Address<9:6>
PS0 = 0
PS1 = 0
<15:8> RAM Segment 0 Beginning Address<5:0>
RAM Segment 0
Final Address<9:8>
PS0 = 0
PS1 = 0
<23:16> RAM Segment 0 Final Address<7:0>
PS0 = 0
PS1 = 0
<31:24> RAM Segment 0 Address Ramp Rate<15:8>
PS0 = 0
PS1 = 0
<39:32> RAM Segment 0 Address Ramp Rate<7:0>
PS0 = 0
PS1 = 0