Datasheet

AD9954
Rev. B | Page 20 of 40
The last method in which the sweep ramp rate timer can be
reset is changing from inactive linear sweep mode to active
linear sweep mode using the linear sweep enable bit (CFR1<21>).
For methods two and three, the ramp rate timer loads a value
determined by the state of PS0 (0 = FSRRW, 1 = RSRRW).
Power-Down Functions of the AD9954
The AD9954 supports an externally controlled (or hardware)
power-down feature as well as software-programmable power-
down bits capable of individually powering down specific unused
circuit blocks.
Software-controlled power-down enables individual powering
down of the DAC, comparator, PLL, input clock circuitry, and
the digital logic (CFR1<7:4>). With the exception of CFR1<6>,
these bits are superseded when the externally controlled power-
down pin (PWRDWNCTL) is high. External power-down
control is supported on the AD9954 via the PWRDWNCTL
input pin. When the PWRDWNCTL input pin is high, the
AD9954 enters a power-down mode based on the CFR1<3> bit.
When the PWRDWNCTL input pin is low, it operates normally.
See CFR1<3> in Table 12 for details.
Table 9 details the logic level for each power-down bit that
drives out of the AD9954 core logic to the analog section and
the digital clock generation section of the chip for the external
power-down operation.
Table 9. Power-Down Control Functions
Control Mode Active Description
PWRDWNCTL = 0, CFR1<3> don’t care Software control
Digital power-down = CFR1<7>
Comparator power-down = CFR1<6>
DAC power-down = CFR1<5>
Clock input power-down = CFR1<4>
PWRDWNCTL = 1, CFR1<3> = 0
External control, fast recovery
power-down mode
Digital power-down = 1’b1
Comparator power-down = 1’b0 or CFR1<6>
DAC power-down = 1’b0
Clock input power-down = 1’b0
PWRDWNCTL = 1, CFR1<3> = 1
External control, full power-down
mode
Digital power-down = 1’b1
Comparator power-down = 1’b1
DAC power-down = 1’b1
Clock input power-down = 1’b1