Datasheet
AD9953
Rev. A | Page 26 of 32
There are two phases to a communication cycle with the
AD9953. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9953, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9953 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is read or write and the serial address of the register
being accessed.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9953. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between
f bytes transferred
during Phase 2 of the communication cycle is a function of the
register being accessed. For example, when accessing the Control
Function Register No. 2, which is three bytes wide, Phase 2 requires
that three bytes be transferred. If accessing the frequency tuning
word, which is four bytes wide, Phase 2 requires that four bytes
be transferred. After transferring all data bytes per the
instruction, the communication cycle is completed.
At the completion of any communication cycle, the AD9953
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9953 is registered on the rising edge of
SCLK. All data is driven out of the AD9953 on the falling ge
23 through Figure 26 are useful in VOEFSTUBOE
ing the general operation of the AD9953 serial port.
th
e AD9953 of SCLK. Figure
and the system controller. The number o
ed
03374-0-008
I
6
I
5
I
4
I
3
I
2
I
7
INSTRUCTION CYCLE
I
1
I
0
D D
5
D
4
D
3
D
2
D
1
D
07
D
6
SCLK
SDIO
DATA TRANSFER CYCLE
CS
ng—Clock Stall Low Figure 23. Serial
Port Write Timi
03374-0-009
I
6
I
5
I
4
I
3
II
7
INSTRUCTION CYCLE DATA TRANSFER CYCLE
2
I
1
I
0
DON'T CARE
SCLK
SDIO
D D
O 5
D
O 4
D
O 3
D
O 2
D
O 1
D
O 0O 7
D
O 6
SDO
CS
iming—Clock Stall Low Figure 24. 3-Wire Serial
Port Read T
03374-0-010
I
6
I
5
I
4
I
3
I
2
I
7
INSTRUCTION CYCLE
I
1
D
0
I
0
D D D D DD D
5 4 3 2 17 6
SCLK
SDIO
DATA TRANSFER CYCLE
CS
Write TimiFigure 25. Serial Port
ng—Clock Stall High
03374-0-011
I
6
I
5
I
4
I
3
II
7 2
I
1
I
0
D
O 5
D
O 4
D
O 3
D
O 2
D
O 1
D
O 0
D
O 7
D
O 6
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
CS
ming—Clock Stall High Figure 26. 2-Wire Seri
al Port Read Ti