Datasheet

AD9953
Rev. A | Page 17 of 32
ing mode).
igured as
ctive.
1. All non-IO digital functionality is suspended,
: Not Used
Down Bit
he clock input circuitry is enabled for
d the
External Power-Down Mode
ode,
high, the digital logic
red down. The DAC bias
the
CTL
ons are powered down. This includes
ake a significant amount of time to
YNC_CLK Disable Bit
static Logic 0
ate to keep noise generated by the digital circuitry at a
s
ming.
ntrol the various functions, features, and
og sections
ot Used
Bit
o use the auto-
e for SYNC_CLK inputs beyond 50 MHz,
chronizing Multiple AD9953s
ff.
nc function is enabled.
SYNC_IN pin will
cle. Unlike the software manual sync enable bit, this
is
red. See the
n for details.
,
T
y. The oscillator will respond to crystals in
ord controls the multiplier value out of the clock-
k. Valid values are decimal 4 to 20 (0x04 to
tside this range will bypass the clock
op (PLL) section for details.
nge of
100 MHz to 250 MHz. When CFR2<2> == 1, the VCO operates
in a range of 250 MHz to 400 MHz.
CFR1<9>: SDIO Input Only
CFR1<9> = 0 (default). The SDIO pin has bidirectional
operation (2-wire serial programm
CFR1<9> = 1. The serial data I/O pin (SDIO) is conf
an input only pin (3-wire serial programming mode).
CFR1<8>: LSB First
CFR1<8> = 0 (default). MSB first format is active.
CFR1<8> = 1. The serial interface accepts serial data in LSB
first format.
CFR1<7>: Digital Power-Down Bit
CFR1<7> = 0 (default). All digital functions and clocks are a
CFR1<7> =
lowering the power significantly.
CFR1<6>
CFR1<5>: DAC Power-Down Bit
CFR1<5> = 0 (default). The DAC is enabled for operation.
CFR1<5> = 1. The DAC is disabled and is in its lowest power
dissipation state.
CFR1<4>: Clock Input Power-
CFR1<4> = 0 (default). T
operation.
CFR1<4> = 1. The clock input circuitry is disabled an
device is in its lowest power dissipation state.
CFR1<3>:
CFR1<3> = 0 (default). The external power-down mode
selected is the rapid recovery power-down mode. In this m
when the PWRDWNCTL input pin is
and the DAC digital logic are powe
circuitry, PLL, oscillator, and clock input circuitry are not
powered down.
CFR1<3> = 1. The external power-down mode selected is
full power-down mode. In this mode, when the PWRDWN
nctiinput pin is high, all fu
the DAC and PLL, which t
power up.
CFR1<2>: Not Used
CFR1<1>: S
CFR1<1> = 0 (default). The SYNC_CLK pin is active.
e SYNC_CLK pin assumes a CFR1<1> = 1. Th
st
minimum. However, the synchronization circuitry remain
active (internally) to maintain normal device ti
CFR1<0>: Not Used, Leave at 0
Control Function Register No. 2 (CFR2)
The CFR2 is used to co
modes of the AD9953, primarily related to the anal
of the chip.
CFR2<23:12>: N
CFR2<11>: High Speed Sync Enable
CFR2<11> = 0 (default). The high speed sync enhancement is off.
CFR2<11> = 1. The high speed sync enhancement is on. This
bit should be set when attempting t
synchronization featur
(200 MSPS SYSCLK). See the Syn
section for details.
CFR2<10>: Hardware Manual Sync Enable Bit
CFR2<10> = 0 (default). The hardware manual sync function is o
CFR2<10> = 1. The hardware manual sy
While this bit is set, a rising edge on the
cause the device to advance the SYNC_CLK rising edge by one
REFCLK cy
bit does not self clear. Once the hardware manual sync mode
enabled, it will stay enabled until this bit is clea
Synchronizing Multiple AD9953s sectio
CFR2<9>: CRYSTAL OUT Enable Bit
CFR2<9> = 0 (default). The CRYSTAL OUT pin is inactive.
CFR2<9> = 1. The CRYSTAL OUT pin is active. When active
the crystal oscillator circuitry output drives the CRYSTAL OU
pin, which can be connected to other devices to produce a
reference frequenc
the range of 20 MHz to 30 MHz.
CFR2<8>: Not Used
CFR2<7:3>: Reference Clock Multiplier Control Bits
This 5-bit w
multiplier (PLL) bloc
0x14). Values entered ou
multiplier. See the Phase-Locked Lo
CFR2<2>: VCO Range Control Bit
This bit is used to control the range setting on the VCO.
When CFR2<2> == 0 (default), the VCO operates in a ra