400 MSPS, 14-Bit, 1.8 V CMOS Direct Digital Synthesizer AD9953 FEATURES PLL REFCLK multiplier (4× to 20×) Internal oscillator, can be driven by a single crystal Phase modulation capability Multichip synchronization 400 MSPS internal clock speed Integrated 14-bit DAC 32-bit tuning word Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output) Excellent dynamic performance >80 dB SFDR @ 160 MHz (±100 kHz offset) AOUT Serial I/O control 1.
AD9953 TABLE OF CONTENTS Features .............................................................................................. 1 Component Blocks ..................................................................... 12 Applications ....................................................................................... 1 Modes of Operation ................................................................... 19 Revision History .............................................................................
AD9953 GENERAL DESCRIPTION The AD9953 is a direct digital synthesizer (DDS) featuring a 14-bit DAC operating up to 400 MSPS. The AD9953 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 200 MHz. The AD9953 includes an integrated 1024 × 32 static RAM to support flexible frequency sweep capability in several modes.
AD9953 ELECTRICAL SPECIFICATIONS Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, RSET = 3.92 kΩ, External Reference Clock Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND.
AD9953 Parameter TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulse Width Low Minimum Clock Pulse Width High Maximum Clock Rise/Fall Time Minimum Data Setup Time DVDD_I/O = 3.3 V Minimum Data Setup Time DVDD_I/O = 1.8 V Minimum Data Hold Time Maximum Data Valid Time Wake-Up Time 2 Minimum Reset Pulse Width High I/O UPDATE (PS0/PS1) to SYNC_CLK Setup Time DVDD_I/O = 3.3 V I/O UPDATE (PS0/PS1) to SYNC_CLK Setup Time DVDD_I/O = 1.
AD9953 ABSOLUTE MAXIMUM RATINGS Table 2. Rating 150°C 4V 2V –0.7 V to +5.25 V –0.7 V to +2.2 V 5 mA –65°C to +150°C –40°C to +105°C 300°C 38°C/W 15°C/W DIGITAL INPUTS ESD CAUTION DAC OUTPUTS DVDD_I/O IOUT IOUT INPUT AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING ESD DIODES MAY COUPLE DIGITAL NOISE ONTO POWER PINS. MUST TERMINATE OUTPUTS TO AVDD. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. Figure 2. Equivalent Input and Output Circuits Rev.
AD9953 PS0 OSK SYNC_CLK SYNC_IN DVDD_I/O DGND SDIO SCLK CS SDO IOSYNC 48 47 46 45 44 43 42 41 40 39 38 37 I/O UPDATE 1 36 RESET DVDD 2 35 PWRDWNCTL DGND 3 34 DVDD AVDD 4 33 DGND AGND 5 32 AGND AVDD 6 31 AGND AGND 7 30 AGND OSC/REFCLK 8 29 AVDD OSC/REFCLK 9 28 AGND CRYSTAL OUT 10 27 AVDD CLKMODESELECT 11 26 AGND LOOP_FILTER 12 25 AVDD AD9953 13 14 15 16 17 18 19 20 21 22 23 24 AVDD AGND AGND AVDD AGND AVDD AVDD IOUT IOU
AD9953 PIN FUNCTION DESCRIPTIONS Table 3. 48-Lead TQFP/EP Pin No. 1 Mnemonic I/O UPDATE I/O I 2, 34 3, 33, 42 4, 6, 13, 16, 18, 19, 25, 27, 29 5, 7, 14, 15, 17, 22, 26, 32 8 DVDD DGND AVDD I I I Description The rising edge transfers the contents of the internal buffer memory to the I/O registers. This pin must be set up and held around the SYNC_CLK output signal. Digital Power Supply Pins (1.8 V). Digital Power Ground Pins. Analog Power Supply Pins (1.8 V). AGND I Analog Power Ground Pins.
AD9953 TYPICAL PERFORMANCE CHARACTERISTICS REF 0dBm 0 PEAK 1R LOG –10 10dB/ MKR1 98.0MHz –70.68dB ATTEN 10dB REF 0dBm 0 PEAK LOG –10 10dB/ –20 –30 MARKER 100.000000MHz –70.68dB –50 –60 W1 S2 S3 FC –70 AA –80 –60 W1 S2 S3 FC –70 AA –80 03374-0-016 1 –90 –100 CENTER 100MHz #RES BW 3kHz VBW 3kHz –90 –100 SPAN 200MHz SWEEP 55.56 s (401 PTS) CENTER 100MHz #RES BW 3kHz Figure 4.
AD9953 REF –4dBm 0 PEAK LOG –10 10dB/ ATTEN 10dB 1 MKR1 1.105MHz –5.679dBm REF –4dBm 0 PEAK LOG –10 10dB/ –20 –20 –30 –30 MARKER 1.105000MHz –5.679dBm –40 –50 –40 –50 03374-0-022 –90 ST –100 CENTER 1.105MHz #RES BW 30Hz VBW 30Hz SPAN 2MHz SWEEP 199.2 s (401 PTS) –90 ST –100 SPAN 2MHz SWEEP 199.2 s (401 PTS) CENTER 80.25MHz #RES BW 30Hz Figure 10. FOUT = 1.1 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz REF 0dBm 0 PEAK LOG 10dB/ –10 Figure 13. FOUT = 80.
AD9953 Figure 16. Residual Phase Noise with FOUT = 159.5 MHz, FCLK = 400 MSPS (Green), 4 × 100 MSPS (Red), and 20 × 20 MSPS (Blue) Figure 18. Residual Phase Noise with FOUT = 9.5 MHz, FCLK = 400 MSPS (Green), 4 ×100 MSPS (Red), and 20 × 20 MSPS (Blue) t1 = 3.156ns t2 = 3.04ns Δt = –116.0PS 1/Δt = –8.621GHz FALL (R1) = 396.4PS RISE(R2) = 464.3PS R1 R2 CH1 200mVΩ M 200PS 20.0GS/S A CH1 708mV 03374-0-030 03374-0-031 1 IT 4.0PS/PT 3.1ns REF2 200mV 500ns Figure 17.
AD9953 THEORY OF OPERATION COMPONENT BLOCKS DDS Core Clock Input The output frequency (fO) of the DDS is a function of the frequency of the system clock (SYSCLK), the value of the frequency tuning word (FTW), and the capacity of the accumulator (232, in this case). The exact relationship is given below with fS defined as the frequency of SYSCLK. The AD9953 supports various clock methodologies.
AD9953 DAC Output Serial IO Port The AD9953 incorporates an integrated 14-bit current output DAC. Unlike most DACs, this output is referenced to AVDD, not AGND. The AD9953 serial port is a flexible, synchronous serial communications port that allows easy interface to many industrystandard microcontrollers and microprocessors. The serial I/O port is compatible with most synchronous transfer formats, including both the Motorola 6905/11 SPI® and Intel® 8051 SSR protocols.
AD9953 Table 5. Register Map Register Name (Serial Address) Bit Range <7:0> Control Function Register No.1 (CFR1) (0x00) <15:8> <23:16> <31:24> Control Function Register No.
AD9953 Register Name (Serial Address) Bit Range <7:0> RAM Segment Control Word No. 0 (RSCW0) (0x07) <15:8> <23:16> <31:24> <39:32> <7:0> RAM Segment Control Word No. 1 (RSCW1) (0x08) <15:8> <23:16> <31:24> <39:32> <7:0> RAM Segment Control Word No. 2 (RSCW2) (0x09) <15:8> <23:16> <31:24> <39:32> <7:0> RAM Segment Control Word No.
Control Register Bit Descriptions Control Function Register. No. 1 (CFR1) The CFR1 is used to control the various functions, features, and modes of the AD9953. The functionality of each bit is below. CFR1<31>: RAM Enable Bit CFR1<31> = 0 (default). The RAM is powered down to conserve power. Single-tone mode of operation is active. CFR1<31> = 1. If CFR1<31> is active, the RAM is enabled for operation.
AD9953 minimum. However, the synchronization circuitry remains active (internally) to maintain normal device timing. CFR1<9>: SDIO Input Only CFR1<9> = 0 (default). The SDIO pin has bidirectional operation (2-wire serial programming mode). CFR1<0>: Not Used, Leave at 0 CFR1<9> = 1. The serial data I/O pin (SDIO) is configured as an input only pin (3-wire serial programming mode). CFR1<8>: LSB First CFR1<8> = 0 (default). MSB first format is active. Control Function Register No.
AD9953 CFR2<1:0>: Charge Pump Current Control Bits These bits are used to control the current setting on the charge pump. The default setting, CFR2<1:0>, sets the charge pump current to the default value of 75 μA. For each bit added (01, 10, 11), 25 μA of current is added to the charge pump current: 100 μA, 125 μA, and 150 μA.
AD9953 input of the phase accumulator and supplies the frequency tuning word(s) for the device. When the RAM output drives the phase accumulator, the phase offset word (POW, Address 0x05) drives the phase-offset adder. Similarly, when the RAM output drives the phase offset adder, the frequency tuning word (FTW, Address 0x04) drives the phase accumulator. When CFR1<31> is Logic 0, the RAM is inactive unless being written to via the serial port.
AD9953 If the no-dwell bit is clear when the RAM address generator equals the final address, the generator stops incrementing as the terminal frequency has been reached. The sweep is complete and does not restart until an I/O UPDATE or change in profile is detected to enable another sweep from the beginning to the final RAM address as described above. If the no-dwell bit is set when the RAM address generator equals the final address, after the next ramp rate timer cycle the phase accumulator is cleared.
AD9953 next address, and the timer reloads the ramp rate bits and continues counting down. This sequence continues until the RAM address generator has incremented to an address equal to the RAM segment final address bits of the current RSCW. Upon reaching this terminal address, the RAM address generator reloads the RAM segment beginning address bits and the sequence repeats. The sequence of circulating through the specified RAM addresses repeats for as long as the part is programmed for this mode.
AD9953 PROGRAMMING AD9953 FEATURES Phase Offset Control A 14-bit phase offset (θ) may be added to the output of the phase accumulator by means of the control registers. This feature provides the user with two different methods of phase control. The first method is a static phase adjustment where a fixed phase offset is loaded into the appropriate phase offset register and left unchanged. The result is that the output signal is offset by a constant angle relative to the nominal signal.
AD9953 OSK Ramp Rate Timer The OSK ramp rate timer is a loadable down counter, which generates the clock signal to the 14-bit counter that generates the internal scale factor. The ramp rate timer is loaded with the value of the ASFR every time the counter reaches 1 (decimal). This load and countdown operation continues for as long as the timer is enabled, unless the timer is forced to load before reaching a count of 1.
AD9953 External Shaped On-Off Keying Mode Operation coupled with SYNC_CLK is used to transfer internal buffer contents into the control registers of the device. The combination of the SYNC_CLK and I/O UPDATE pins provides the user with constant latency relative to SYSCLK, and also ensures phase continuity of the analog output signal when a new tuning word or phase offset value is asserted. Figure 21 demonstrates an I/O UPDATE timing cycle and synchronization.
AD9953 SYSCLK A B A B SYNC_CLK I/O UPDATE DATA IN REGISTERS DATA 1 DATA 2 DATA 3 DATA 0 DATA 1 THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE I/O BUFFERS AT POINT B. DATA 2 03357-007 DATA IN I/O BUFFERS Figure 22. I/O Synchronization Timing Diagram Synchronizing Multiple AD9953s The AD9953 allows easy synchronization of multiple AD9953s.
AD9953 There are two phases to a communication cycle with the AD9953. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9953, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9953 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle.
AD9953 INSTRUCTION BYTE The instruction byte contains the following information: Table 9. MSB R/W D6 X D5 X D4 A4 D3 A3 R/W—Bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. Logic High indicates read operation. Logic 0 indicates a write operation. X, X—Bits 6 and 5 of the instruction byte are Don’t Care.
AD9953 When the CFR1<3> bit is 0 and the PWRDWNCTL input pin is high, the AD9953 is put into a fast recovery power-down mode. In this mode, the digital logic and the DAC digital logic are powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry is not powered down. When the CFR1<3> bit is high, and the PWRDWNCTL input pin is high, the AD9953 is put into the full power-down mode. In this mode, all functions are powered down.
AD9953 SUGGESTED APPLICATION CIRCUITS FREQUENCY TUNING WORD MODULATED/ DEMODULATED SIGNAL RF/IF INPUT PHASE OFFSET WORD 1 I/I-BAR BASEBAND 03357-0-003 REFCLK LPF AD9953 REFCLK CRYSTAL AD9953 DDS IOUT IOUT LPF REFCLK CRYSTAL OUT SYNC OUT RF OUT Figure 27. Synchronized LO for Up Conversion/Down Conversion SYNC IN AD9953 DDS LOOP FILTER VCO FILTER IOUT LPF REFCLK AD9953 TUNING WORLD IOUT FREQUENCY TUNING WORD PHASE OFFSET WORD 2 Q/Q-BAR BASEBAND Figure 29.
AD9953 OUTLINE DIMENSIONS 9.00 BSC SQ 1.20 MAX BOTTOM VIEW (PINS UP) 37 36 48 1 37 36 48 1 7.00 BSC SQ PIN 1 3.50 SQ TOP VIEW (PINS DOWN) 0° MIN 1.05 1.00 0.95 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY EXPOSED PAD 12 13 VIEW A 25 24 25 24 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW 12 13 0.27 0.22 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
AD9953 NOTES Rev.
AD9953 NOTES ©2004–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03374-0-5/09(A) Rev.
