Datasheet
AD9952
Rev. B | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCLK
SDIO
SDO
CS
3
4
8
9
1
36
35
34
33
32
31
30
29
28
7
6
2
5
10
11
12
25
26
27
374142434445464748
DACBP
AGND
IOUT
IOUT
AVDD
AGND
AVDD
AVDD
AVDD
AGND
AGND
AGND
AGND
AVDD
AVDD
AVDD
COMP_OUT
COMP_IN
COMP_IN
DGND
DGND
DVDD
PWRDWNCTL
RESET
IOSYNC
DVDD_I/O
SYNC_IN
SYNC_CLK
OSK
DGND
DGND
I/O UPDATE
DVDD
DGND
AVDD
AGND
AVDD
AGND
REFCLK
REFCLK
CRYSTAL OUT
CLKMODESELECT
LOOP_FILTER
AD9952
TOP VIEW
(Not to Scale)
40 39 38
DAC_R
SET
13 14 15 16 17 18 19 20 21 22 23 24
03358-002
Figure 2. Pin Configuration
Note that the exposed paddle on the bottom of the package is a ground connection for the DAC and must be attached to AGND in
any board layout. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or 3.3 V; however, the DVDD pins (Pin 2 and Pin 34) can
only be powered to 1.8 V.
Table 3. 48-Lead TQFP/EP
Pin No. Mnemonic I/O Description
1 I/O UPDATE I The rising edge transfers the contents of the internal buffer memory to the I/O registers. This pin
must be set up and held around the SYNC_CLK output signal.
2, 34 DVDD I Digital Power Supply Pins (1.8 V).
3, 33, 42,
47, 48
DGND I Digital Power Ground Pins.
4, 6, 13,
16, 18, 19,
25, 27, 29
AVDD I Analog Power Supply Pins (1.8 V).
5, 7, 14,
15, 17, 22,
26, 32
AGND I Analog Power Ground Pins.
8
REFCLK
I
Complementary Reference Clock/Oscillator Input. When the REFCLK port is operated in single-
ended mode,
REFCLK
should be decoupled to AVDD with a 0.1 µF capacitor.
9 REFCLK
I Reference Clock/Oscillator Input. See the Clock Input section for details on the oscillator/REFCLK
operation.
10 CRYSTAL OUT O Output of the Oscillator Section.
11 CLKMODESELECT I Control Pin for the Oscillator Section. When high, the oscillator section is enabled. When low, the
oscillator section is bypassed.
12 LOOP_FILTER I This pin provides the connection for the external zero compensation network of the REFCLK
multiplier’s PLL loop filter. The network consists of a 1 k Ω resistor in series with a 0.1 µF capacitor
tied to AVDD.
20
IOUT
O Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND.
21 IOUT O DAC Output. Should be biased through a resistor to AVDD, not AGND.