Datasheet

AD9945
–11–
CCD MODE TIMING
N N+1 N+2 N+9 N+10
t
ID
t
ID
t
S1
t
OD
N–10 N– 9 N– 8 N– 1 N
NOTES
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
SHP
SHD
DATACLK
OUTPUT
DATA
CCD
SIGNAL
t
S2
t
CP
Figure 8. CCD Mode Timing
CCD
SIGNAL
EFFECTIVE PIXELS
CLPOB
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKING
DUMMY PIXELS EFFECTIVE PIXELS
PBLK
NOTES
1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
OUTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA DUMMY BLACK EFFECTIVE DATA
Figure 9. Typical CCD Mode Line Clamp Timing
REV.
C